Patents by Inventor Keisuke Kikutani

Keisuke Kikutani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930665
    Abstract: A semiconductor device of an embodiment includes a control circuit arranged on a substrate, a first conductive layer arranged on the control circuit and containing a first element as a main component, a multilayer structure arranged on the first conductive layer and configured such that multiple second conductive layers and multiple insulating layers are alternately stacked on each other, a memory layer penetrating the multilayer structure and reaching the first conductive layer at a bottom portion, a first layer arranged between the control circuit and the first conductive layer and containing the first element as a main component, and a second layer arranged between the control circuit and the first layer and containing, as a main component, a second element different from the first element.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: February 23, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Kosuke Horibe, Kei Watanabe, Toshiyuki Sasaki, Tomo Hasegawa, Soichi Yamazaki, Keisuke Kikutani, Jun Nishimura, Hisashi Harada, Hideyuki Kinoshita
  • Patent number: 10903238
    Abstract: A semiconductor device includes a substrate, a stacked body provided on the substrate, a first insulator dividing the stacked body in a second direction crossing the first direction, a second insulator adjacent to the first insulator and dividing the stacked body in the second direction, a first hole, and a first insulating member. In the stacked body, a plurality of layers are stacked in a first direction perpendicular to the upper surface of the substrate. The first hole penetrates the stacked body and the first insulator in the first direction. The first insulating member penetrates the stacked body and the second insulator in the first direction and is adjacent to the first hole via a first electrode in a third direction crossing the first direction and the second direction, and has an opening diameter larger than that of the first insulator.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: January 26, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsumi Yamamoto, Keisuke Kikutani
  • Publication number: 20210020439
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film on the first film. The second film includes fluoride of a first metal element having a first boiling point of 800° C. or higher and fluoride of a second metal element having a second boiling point of 800° C. or higher. The second metal element is different from the first metal element. The method further includes etching the first film using the second film as an etching mask and etching gas that includes fluorine.
    Type: Application
    Filed: February 27, 2020
    Publication date: January 21, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Soichi YAMAZAKI, Kazuhito FURUMOTO, Kosuke HORIBE, Keisuke KIKUTANI, Atsuko SAKATA
  • Patent number: 10763122
    Abstract: A method of manufacturing a semiconductor device includes forming a mask layer including aluminum or an aluminum compound on a layer to be etched comprising at least one first metal selected from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium. The method of manufacturing a semiconductor device further includes patterning the mask layer, and etching the layer to be etched by using the patterned mask layer to form a hole or a groove in the layer to be etched.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Soichi Yamazaki, Kazuhito Furumoto, Kosuke Horibe, Keisuke Kikutani, Atsuko Sakata, Junichi Wada, Toshiyuki Sasaki
  • Publication number: 20200235117
    Abstract: A semiconductor device of an embodiment includes a control circuit arranged on a substrate, a first conductive layer arranged on the control circuit and containing a first element as a main component, a multilayer structure arranged on the first conductive layer and configured such that multiple second conductive layers and multiple insulating layers are alternately stacked on each other, a memory layer penetrating the multilayer structure and reaching the first conductive layer at a bottom portion, a first layer arranged between the control circuit and the first conductive layer and containing the first element as a main component, and a second layer arranged between the control circuit and the first layer and containing, as a main component, a second element different from the first element.
    Type: Application
    Filed: August 9, 2019
    Publication date: July 23, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kosuke HORIBE, Kei Watanabe, Toshiyuki Sasaki, Tomo Hasegawa, Soichi Yamazaki, Keisuke Kikutani, Jun Nishimura, Hisashi Harada, Hideyuki Kinoshita
  • Publication number: 20200161331
    Abstract: A semiconductor device includes a substrate, a stacked body provided on the substrate, a first insulator dividing the stacked body in a second direction crossing the first direction, a second insulator adjacent to the first insulator and dividing the stacked body in the second direction, a first hole, and a first insulating member. In the stacked body, a plurality of layers are stacked in a first direction perpendicular to the upper surface of the substrate. The first hole penetrates the stacked body and the first insulator in the first direction. The first insulating member penetrates the stacked body and the second insulator in the first direction and is adjacent to the first hole via a first electrode in a third direction crossing the first direction and the second direction, and has an opening diameter larger than that of the first insulator.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Katsumi YAMAMOTO, Keisuke KIKUTANI
  • Patent number: 10573660
    Abstract: A semiconductor device includes a substrate, a stacked body provided on the substrate, a first insulator dividing the stacked body in a second direction crossing the first direction, a second insulator adjacent to the first insulator and dividing the stacked body in the second direction, a first hole, and a first insulating member. In the stacked body, a plurality of layers are stacked in a first direction perpendicular to the upper surface of the substrate. The first hole penetrates the stacked body and the first insulator in the first direction. The first insulating member penetrates the stacked body and the second insulator in the first direction and is adjacent to the first hole via a first electrode in a third direction crossing the first direction and the second direction, and has an opening diameter larger than that of the first insulator.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 25, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Katsumi Yamamoto, Keisuke Kikutani
  • Patent number: 10515797
    Abstract: According to one embodiment, a method for producing a semiconductor device includes forming a first film on a substrate. A second film is formed on the first film. A recess is formed in the second film. First processing by which a third film is formed on the second film to form a side face of the recess with the second film and second processing by which the first film exposed in the recess is processed by using the second and third films, are executed one or more times. In relation to an N-th (N is an integer greater than or equal to 1) first processing, before the third film is formed on the second film, a surface inclined with respect to the side face of the recess is formed above the side face of the recess.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: December 24, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhito Furumoto, Keisuke Kikutani, Soichi Yamazaki
  • Publication number: 20190296036
    Abstract: A semiconductor device includes a substrate, a stacked body provided on the substrate, a first insulator dividing the stacked body in a second direction crossing the first direction, a second insulator adjacent to the first insulator and dividing the stacked body in the second direction, a first hole, and a first insulating member. In the stacked body, a plurality of layers are stacked in a first direction perpendicular to the upper surface of the substrate. The first hole penetrates the stacked body and the first insulator in the first direction. The first insulating member penetrates the stacked body and the second insulator in the first direction and is adjacent to the first hole via a first electrode in a third direction crossing the first direction and the second direction, and has an opening diameter larger than that of the first insulator.
    Type: Application
    Filed: August 20, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Katsumi YAMAMOTO, Keisuke KIKUTANI
  • Patent number: 10418376
    Abstract: A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. The first portions extend in a first direction and are arranged along a second direction that intersects with the first direction. The plurality of semiconductor members are arranged along the first direction between the first portions and extending in a third direction. The third direction intersects with a plane containing the first direction and the second direction. The charge storage member is disposed between each of the semiconductor members and each of the first portions. The second portion is disposed between the semiconductor members.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Koichi Sakata, Yuta Watanabe, Keisuke Kikutani, Satoshi Nagashima, Fumitaka Arai, Toshiyuki Iwamoto
  • Publication number: 20190259609
    Abstract: According to one embodiment, a method for producing a semiconductor device includes forming a first film on a substrate. A second film is formed on the first film. A recess is formed in the second film. First processing by which a third film is formed on the second film to form a side face of the recess with the second film and second processing by which the first film exposed in the recess is processed by using the second and third films, are executed one or more times. In relation to an N-th (N is an integer greater than or equal to 1) first processing, before the third film is formed on the second film, a surface inclined with respect to the side face of the recess is formed above the side face of the recess.
    Type: Application
    Filed: July 10, 2018
    Publication date: August 22, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhito FURUMOTO, Keisuke KIKUTANI, Soichi YAMAZAKI
  • Patent number: 10332906
    Abstract: A dry etching method includes a process of, while continuously applying bias power using an ion species to a material to be processed including a first conductive member, a first insulating film provided on the first conductive member, a second conductive member provided on the first insulating film, and a second insulating film provided on the second conductive member, dry etching the second insulating film to expose the second conductive member. A time for which the bias power is continuously applied is set to 50 microseconds or less and a duty ratio of the bias power is set to 50% or less.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kaori Narumiya, Hisataka Hayashi, Keisuke Kikutani, Akio Ui, Yosuke Sato
  • Patent number: 10325920
    Abstract: A method for manufacturing a semiconductor device includes forming a first mask layer having a first opening on an underlying layer; forming a first layer in a space where the underlying layer is selectively removed via the first opening; forming a second mask layer on the first mask layer and the first layer, the second mask layer having a second opening crossing the first opening; and selectively removing the first layer at a portion where the first opening and the second opening cross. At least one of the first and second mask layers having openings including the first or second opening, the openings being arranged in the first mask layer along a first direction, and/or being arranged in the second mask layer along a second direction, the first opening crossing the second opening in the first direction, and the second opening crossing the first opening in the second direction.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: June 18, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chihiro Abe, Keisuke Kikutani, Katsumi Yamamoto, Tomoya Oori
  • Patent number: 10103155
    Abstract: A semiconductor memory device according to an embodiment, includes a first semiconductor member, a second semiconductor member, an insulating member, a plurality of electrode films, a first electrode, and a second electrode. The first semiconductor member and the second semiconductor member are separated in a first direction and extending in a second direction. The second direction crosses the first direction. The insulating member is provided between the first semiconductor member and the second semiconductor member. The plurality of electrode films are arranged to be separated from each other along the second direction. Each of the electrode films surrounds the first semiconductor member, the second semiconductor member, and the insulating member when viewed from the second direction. The first electrode is provided between the first semiconductor member and the electrode film. The second electrode is provided between the second semiconductor member and the electrode film.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: October 16, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kohei Sakaike, Toshiyuki Iwamoto, Tatsuya Kato, Keisuke Kikutani, Fumitaka Arai, Satoshi Nagashima, Koichi Sakata, Yuta Watanabe
  • Publication number: 20180261466
    Abstract: A method of manufacturing a semiconductor device includes forming a mask layer including aluminum or an aluminum compound on a layer to be etched comprising at least one first metal selected from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium. The method of manufacturing a semiconductor device further includes patterning the mask layer, and etching the layer to be etched by using the patterned mask layer to form a hole or a groove in the layer to be etched.
    Type: Application
    Filed: September 5, 2017
    Publication date: September 13, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Soichi YAMAZAKI, Kazuhito FURUMOTO, Kosuke HORIBE, Keisuke KIKUTANI, Atsuko SAKATA, Junichi WADA, Toshiyuki SASAKI
  • Patent number: 10056400
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, a stacked body, and a first insulating film. The stacked body is provided on the semiconductor substrate. The stacked body includes first films, and second films being conductive. The first films and the second films are stacked alternately. The first insulating film extends in a stacking direction of the stacked body. The second films include a first portion and a second portion. The first portion is positioned between the first films. The second portion has a surface contacting the first insulating film in a direction perpendicular to the stacking direction.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: August 21, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fumie Kikushima, Keisuke Kikutani
  • Publication number: 20180145086
    Abstract: A dry etching method includes a process of, while continuously applying bias power using an ion species to a material to be processed including a first conductive member, a first insulating film provided on the first conductive member, a second conductive member provided on the first insulating film, and a second insulating film provided on the second conductive member, dry etching the second insulating film to expose the second conductive member. A time for which the bias power is continuously applied is set to 50 microseconds or less and a duty ratio of the bias power is set to 50% or less.
    Type: Application
    Filed: July 27, 2017
    Publication date: May 24, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kaori NARUMIYA, Hisataka HAYASHI, Keisuke KIKUTANI, Akio UI, Yosuke SATO
  • Patent number: 9966381
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first conductive film provided on a first region of the first insulating film, a second conductive film provided on a second region of the first insulating film, a first stacked body provided on the first conductive film, a second stacked body provided on the second conductive film, a first semiconductor pillar, and two conductive pillars. In the first stacked body, a second insulating film and an electrode film are stacked alternately. In the second stacked body, a third insulating film and a first film are stacked alternately. The two conductive pillars extend in the first direction through the second stacked body, are separated from the second conductive film, sandwich the second conductive film, and are connected at a bottom ends of the second conductive pillars to the semiconductor substrate.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 8, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fumitaka Arai, Tatsuya Kato, Satoshi Nagashima, Katsuyuki Sekine, Yuta Watanabe, Keisuke Kikutani, Atsushi Murakoshi
  • Publication number: 20180097011
    Abstract: A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. The first portions extend in a first direction and are arranged along a second direction that intersects with the first direction. The plurality of semiconductor members are arranged along the first direction between the first portions and extending in a third direction. The third direction intersects with a plane containing the first direction and the second direction. The charge storage member is disposed between each of the semiconductor members and each of the first portions. The second portion is disposed between the semiconductor members.
    Type: Application
    Filed: November 21, 2017
    Publication date: April 5, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Koichi Sakata, Yuta Watanabe, Keisuke Kikutani, Satoshi Nagashima, Fumitaka Arai, Toshiyuki Iwamoto
  • Patent number: 9853050
    Abstract: According to an embodiment, a semiconductor memory device includes a substrate, at least one stacked body, and a first insulating film. The stacked body includes a first end portion positioned at an end in at least one of a first direction and a second direction that crosses the first direction along a surface of the substrate, the plurality of electrode layers being formed into stairs in the first end portion, each of the plurality of electrode layers having a step in the first end portion. The first insulating film is provided on the substrate and includes first and second surfaces, the first and second surfaces surrounding the first end portion, the first surface being crossing a direction that the steps are formed, the second surface being positioned along the direction that the steps are formed.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: December 26, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Keisuke Kikutani