Patents by Inventor Keisuke Nakatsuka

Keisuke Nakatsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210149568
    Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.
    Type: Application
    Filed: December 14, 2020
    Publication date: May 20, 2021
    Applicant: Kioxia Corporation
    Inventors: Yasuhito YOSHIMIZU, Takashi FUKUSHIMA, Tatsuro HITOMI, Arata INOUE, Masayuki MIURA, Shinichi KANNO, Toshio FUJISAWA, Keisuke NAKATSUKA, Tomoya SANUKI
  • Patent number: 11011541
    Abstract: A semiconductor memory device includes a first block and a second block arranged adjacent to each other in a Y direction. Each of the first and second blocks includes conductive layers extended in an X direction, memory trenches between the conductive layers, memory pillars provided across two conductive layers with a memory trench interposed therebetween, and transistors provided between the memory pillars and the conductive layers. One of the conductive layers provided at an end of the first block in the Y direction is electrically connected to one of the conductive layers provided at an end of the second block.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: May 18, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keisuke Nakatsuka, Fumitaka Arai
  • Patent number: 10991713
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: April 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Keisuke Nakatsuka, Fumitaka Arai, Shinya Arai, Yasuhiro Uchiyama
  • Patent number: 10978471
    Abstract: A semiconductor memory device includes first structure bodies and second structure bodies arranged alternately along a first direction. The first structure body includes electrode films arranged along a second direction. The second structure body includes columnar members, first insulating members, and second insulating members. The columnar member includes a semiconductor member extending in the second direction and a charge storage member provided between the semiconductor member and the electrode film. The second insulating members are arranged along a third direction. Lengths in the first direction of the second insulating members are longer than lengths in the first direction of the first insulating members. Positions of the second insulating members in the third direction are different from each other between the second structure bodies adjacent to each other in the first direction. The columnar members and the first insulating members are arranged alternately between the second insulating members.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: April 13, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Keisuke Nakatsuka
  • Publication number: 20210090616
    Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.
    Type: Application
    Filed: December 2, 2020
    Publication date: March 25, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Keisuke NAKATSUKA, Tomoya SANUKI, Takashi MAEDA, Go SHIKATA, Hideaki AOCHI
  • Publication number: 20210082823
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad.
    Type: Application
    Filed: March 3, 2020
    Publication date: March 18, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Nobuyuki MOMO, Keisuke NAKATSUKA
  • Publication number: 20210074638
    Abstract: In one embodiment, a semiconductor device includes a substrate including two element regions that extend in a first direction parallel to a surface of the substrate and are adjacent to each other in a second direction crossing the first direction. The device further includes an interconnection layer provided above the substrate. The device further includes an insulator provided between the substrate and the interconnection layer. The device further includes a plug extending in the second direction and in a third direction crossing the first and second directions in the insulator, provided on each of the element regions, and electrically connected to the element regions and the interconnection layer.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 11, 2021
    Applicant: Kioxia Corporation
    Inventors: Tomoya SANUKI, Keisuke NAKATSUKA, Yasuhito YOSHIMIZU
  • Publication number: 20210020655
    Abstract: A semiconductor memory device according to an embodiment includes a substrate, first to eleventh conductive layers, first and second pillars, and first to fourth insulating regions. The first insulating regions are provided between the third and fifth conductive layers and between the fourth and sixth conductive layers. The second insulating regions are provided between the eighth and tenth conductive layers and between the ninth and eleventh conductive layers. The third insulating region is provided between the third to sixth conductive layers and the eighth to eleventh conductive layers. The fourth insulating region is provided between the second and seventh conductive layers. The fourth insulating region is separated from the third insulating region in a planar view.
    Type: Application
    Filed: February 26, 2020
    Publication date: January 21, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Naoya YOSHIMURA, Keisuke NAKATSUKA
  • Patent number: 10867641
    Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: December 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Keisuke Nakatsuka, Tomoya Sanuki, Takashi Maeda, Go Shikata, Hideaki Aochi
  • Publication number: 20200386461
    Abstract: A double pipe icemaker includes an inner pipe, and an outer pipe provided radially outside the inner pipe and coaxially with the inner pipe. The outer pipe allows a cooling target to flow in the inner pipe and a refrigerant to flow in a space between the inner and outer pipes. The outer pipe has a wall provided with at least one nozzle to jet the refrigerant into the space. The nozzle has a jet port. The jet port may allow the refrigerant to jet in a radial direction including at least an axial direction and a circumferential direction of the inner pipe. A shielding plate may be provided ahead of the jet port in a jetting direction such that the refrigerant hitting the shielding plate expands along a surface of the shielding plate in a radial direction.
    Type: Application
    Filed: January 11, 2019
    Publication date: December 10, 2020
    Inventors: Takahito NAKAYAMA, Ryouji MATSUE, Keisuke NAKATSUKA, Satoru OHKURA, Takeo UENO
  • Publication number: 20200348058
    Abstract: An ice making system includes: a refrigerant circuit that performs a vapor compression refrigeration cycle and that includes a compressor, a condenser that condenses refrigerant discharged from the compressor, a first expansion valve with an adjustable opening degree that decompresses the refrigerant from the condenser, a flooded evaporator that evaporates the refrigerant decompressed by the first expansion valve, and a superheater that imparts a degree of superheating to the refrigerant discharged from the flooded evaporator; a circulation circuit that circulates a medium that is cooled by the flooded evaporator; and a control device that controls the adjustable opening degree of the first expansion valve such that the superheater imparts to the refrigerant discharged from the flooded evaporator a degree of superheating at which dryness of the refrigerant is kept within a predetermined range of less than 1.
    Type: Application
    Filed: December 14, 2018
    Publication date: November 5, 2020
    Applicant: DAIKIN INDUSTRIES, LTD.
    Inventors: Kouichi Kita, Azuma Kondou, Shouhei Yasuda, Keisuke Nakatsuka, Kazuyoshi Nomura, Takeo Ueno
  • Publication number: 20200303395
    Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keisuke NAKATSUKA, Yoshitaka KUBOTA, Tetsuaki UTSUMI, Yoshiro SHIMOJO, Ryota KATSUMATA
  • Publication number: 20200303389
    Abstract: A semiconductor memory device includes first conductive layers stacked on a substrate; second conductive layers stacked on the substrate and apart from the first conductive layer in a direction; third conductive layers stacked on the substrate and electrically connected to the first and second conductive layers; first insulating layers arranged in the direction to sandwich the first conductive layers; second insulating layers arranged in the direction to sandwich the second conductive layers; slit regions that sandwich the third conductive layers; and memory pillars disposed on the first and second insulating layers. The slit region is disposed between an end portion of one of the first insulating layers and an end portion of one of the second insulating layers.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Keisuke NAKATSUKA
  • Publication number: 20200303403
    Abstract: A semiconductor memory device includes a first block and a second block arranged adjacent to each other in a Y direction. Each of the first and second blocks includes conductive layers extended in an X direction, memory trenches between the conductive layers, memory pillars provided across two conductive layers with a memory trench interposed therebetween, and transistors provided between the memory pillars and the conductive layers. One of the conductive layers provided at an end of the first block in the Y direction is electrically connected to one of the conductive layers provided at an end of the second block.
    Type: Application
    Filed: September 3, 2019
    Publication date: September 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keisuke NAKATSUKA, Fumitaka ARAI
  • Publication number: 20200286828
    Abstract: According to one embodiment, a semiconductor memory device includes: a first semiconductor layer including first to third portions which are arranged along a first direction and differ in position from one another in a second direction; a conductive layer including a fourth portion extending in the second direction and a fifth portion extending in the first direction; a first insulating layer between the fourth portion and the first semiconductor layer and between the fifth portion and the first semiconductor layer; a first contact plug coupled to the fourth portion; a second contact plug coupled to the first semiconductor layer in a region where the first insulating layer is formed; a first interconnect; and a first memory cell apart from the fifth portion in the first direction and storing information between the semiconductor layer and the first interconnect.
    Type: Application
    Filed: September 9, 2019
    Publication date: September 10, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji HOSOTANI, Fumitaka ARAI, Keisuke NAKATSUKA, Nobuyuki MOMO, Motohiko FUJIMATSU
  • Patent number: 10748920
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrode films, a semiconductor member, a tunneling insulating film, a charge storage member, and a blocking insulating film. The plurality of electrode films are arranged to be separated from each other along a first direction. The semiconductor member extends in the first direction. The tunneling insulating film is provided between the semiconductor member and the electrode films. The charge storage member is provided between the tunneling insulating film and the electrode films. The blocking insulating film is provided between the charge storage member and the electrode films. The blocking insulating film includes a first film contacting the charge storage film and including carbon-containing silicon oxide, and a second film contacting the electrode films and including hafnium oxide or aluminum oxide.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Keisuke Nakatsuka
  • Publication number: 20200176033
    Abstract: According to one embodiment, a semiconductor memory device includes: a conductive layer including a first portion and a second portion electrically coupled to the first portion; a first contact plug electrically coupled to the first portion; a first semiconductor layer; a first insulating layer between the second portion and the first semiconductor layer, and between the first portion and the first semiconductor layer; a second contact plug coupled to the first semiconductor layer in a region in which the first insulating layer is formed; a first interconnect; and a first memory cell apart from the second portion in the second direction and storing information between the first semiconductor layer and the first interconnect.
    Type: Application
    Filed: September 5, 2019
    Publication date: June 4, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Keiji HOSOTANI, Fumitaka ARAI, Keisuke NAKATSUKA
  • Patent number: 10636809
    Abstract: A semiconductor memory device includes a plurality of electrode films and a plurality of first insulating films stacked alternately along a first direction, a semiconductor member extending in the first direction, a charge storage member provided between the semiconductor member and the electrode films, and a second insulating film provided between the charge storage member and the electrode films. At least one of the plurality of first insulating films includes one or more types of a first material selected from the group consisting of silicon nitride, hafnium oxide, silicon oxynitride, and aluminum oxide.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Keisuke Nakatsuka
  • Publication number: 20200090710
    Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.
    Type: Application
    Filed: March 18, 2019
    Publication date: March 19, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Keisuke NAKATSUKA, Tomoya SANUKI, Takashi MAEDA, Go SHIKATA, Hideaki AOCHI
  • Publication number: 20200091183
    Abstract: A semiconductor memory device includes first structure bodies and second structure bodies arranged alternately along a first direction. The first structure body includes electrode films arranged along a second direction. The second structure body includes columnar members, first insulating members, and second insulating members. The columnar member includes a semiconductor member extending in the second direction and a charge storage member provided between the semiconductor member and the electrode film. The second insulating members are arranged along a third direction. Lengths in the first direction of the second insulating members are longer than lengths in the first direction of the first insulating members. Positions of the second insulating members in the third direction are different from each other between the second structure bodies adjacent to each other in the first direction. The columnar members and the first insulating members are arranged alternately between the second insulating members.
    Type: Application
    Filed: March 12, 2019
    Publication date: March 19, 2020
    Applicant: Toshiba Memory Corporation
    Inventor: Keisuke NAKATSUKA