Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip including a first metal pad and a second metal pad; and a second semiconductor chip including a third metal pad and a fourth metal pad, the third metal pad joined to the first metal pad, the fourth metal pad coupled to the second metal pad via a dielectric layer, wherein the second semiconductor chip is coupled to the first semiconductor chip via the first metal pad and the third metal pad.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and a memory controller. The nonvolatile semiconductor storage device includes at least one memory device including a plurality of memory cells corresponding to a plurality of pages. The memory controller is configured to control the nonvolatile semiconductor storage device. The pages include a first page. The memory controller is configured to: read first data stored in the first page from the nonvolatile semiconductor storage device; correct a fail bit included in the read first data; generate first spare data including information on the fail bit corrected in the read first data; and store the first spare data in the nonvolatile semiconductor storage device.

Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

Abstract: A memory system has a memory cell array having a plurality of strings, the plurality of strings each having a plurality of memory cells connected in series, and a controller configured to perform control of transferring charges to be stored in the plurality of memory cells in the string or transferring charges according to stored data, between potential wells of channels in the plurality of memory cells.

Abstract: A semiconductor storage device has a bit line, a source line, a first memory cell and a second memory cell provided between the bit line and the source line and connected in series, a first word line connected to the first memory cell, a second word line connected to the second memory cell, and a control circuit. The control circuit, when executing a read operation with respect to the first memory cell, supplies a source voltage to the source line, supplies a first voltage to the first word line, and supplies a second voltage to the second word line, and a difference between the source voltage and the second voltage is smaller than a difference between the source voltage and the first voltage.

Abstract: A memory device includes a substrate; first conductors aligned apart from each other in a first direction; a second conductor and a third conductor each extending in a second direction between the substrate and the first conductors, and being aligned apart from each other in the second direction; fourth conductors aligned apart from each other in the first direction on an opposite side of the substrate with respect to the first conductors; a fifth conductor extending in the second direction between the first conductors and the fourth conductors; and a first interconnect coupling between the fifth conductor and the substrate. The first interconnect includes a contact extending in the first direction and passing through the first conductors between the second and third conductors.

Abstract: According to an embodiment, a semiconductor memory device includes a first memory cell array, a second memory cell array, and a row decoder. The first memory cell array includes a first select transistor, a first memory cell, a second select transistor, a first word line, a first select gate line, and a second select gate line. The second memory cell array includes, a third select transistor, a second memory cell, a fourth select transistor, a second word line, a third select gate line, a fourth select gate line. The first word line and the second word line are commonly coupled to the row decoder. The first select gate line, the second select gate line, the third select gate line, and the fourth select gate line are separately coupled to the row decoder.

Abstract: According to one embodiment, there is provided a semiconductor memory device including a first chip, a second chip and a third chip. In the first chip, plural first conductive layers are stacked via a first insulating layer. In the second chip, plural second conductive layers are stacked via a second insulating layer. A number of stack layers in the plural first conductive layers and a number of stack layers in the plural second conductive layers are different from each other.

Abstract: According to one embodiment, in a semiconductor memory device, the first chip has plural memory cells provided at plural intersection positions where the plural first conductive layers and the plural first semiconductor films intersect each other. The second chip has plural memory cells provided at plural intersection positions where the plural second conductive layers and the plural second semiconductor films intersect each other. A first connection configuration and a second connection configuration are insulated from each other. The first connection configuration reaches the third chip from a first conductive layer that a tip of the first semiconductor film reaches among the plural first conductive layers. The second connection configuration reaches the third chip from a second conductive layer that a tip of the second semiconductor film reaches among the plural second conductive layers.

Abstract: A semiconductor storage device of an embodiment includes a substrate, a plurality of first conductive layers, pillar, and a second conductive layer. The plurality of first conductive layers are provided above the substrate, and mutually separated in a first direction. The pillar is provided to penetrate the plurality of the first conductive layers, and includes a first semiconductor layer extending in the first direction. A part of the pillar that intersects with the first conductive layers are functioned as memory cells. The second conductive layer is provided above the plurality of first conductive layers and is in contact with the first semiconductor layer. The second conductive layer is made of a metal or a silicide.

Abstract: A semiconductor device includes a first stacked body and a second stacked body bonded to the first stacked body. The first stacked body includes a first pad provided on a first bonding surface to which the first stacked body and the second stacked body are bonded. The second stacked body includes a second pad bonded to the first pad on the first bonding surface. When a direction from the first stacked body to the second stacked body is defined as a first direction, a direction intersecting with the first direction is defined as a second direction, a direction intersecting with the first direction and the second direction is defined as a third direction, dimensions of the first pad and the second pad in the third direction are defined as PX1 and PX2, respectively, and dimensions of the first pad and the second pad in the second direction are defined as PY1 and PY2, respectively, the dimensions of the first pad and the second pad satisfy at least one of Equations (1) and (2) below.

Abstract: A semiconductor memory device includes a first wiring, a second wiring, a memory pillar, a semiconductor layer, and a contact plug. The second wiring is provided above the first wiring in a first direction. The memory pillar penetrating at least one of a portion of the first wiring or a portion of the second wiring in the first direction. The semiconductor layer extends in the first direction provided in the memory pillar. The contact plug contains a metal and has a lower surface provided in the memory pillar, and the lower surface is in contact with the semiconductor layer below an upper surface of the second wiring.

Abstract: A semiconductor memory device includes a first chip, a second chip, and a multiple of bonding pads. The first chip has a multiple of memory pillars that penetrate a multiple of wiring layers in a first direction. The second chip is bonded to the first chip. The multiple of bonding pads are provided at a bonding face between the first chip and the second chip. The multiple of bonding pads include a first bonding pad that electrically connects a first memory pillar among the multiple of memory pillars to one of a multiple of transistors, and a second bonding pad that neighbors the first bonding pad when seen from the first direction, and which electrically connects a second memory pillar among the multiple of memory pillars to one of the multiple of transistors. The second memory pillar does not neighbor the first memory pillar when seen from the first direction.

Abstract: A method of manufacturing a semiconductor device includes forming a first metal pad in each of a plurality of first regions on a first substrate so that warpage is generated on the first substrate. The method further includes forming a second metal pad in each of a plurality of second regions on a second substrate via a predetermined pattern. The method further includes bonding, after forming the first metal pad and the second metal pad, the first substrate with the second substrate. Moreover, the method further includes: making a correction, at a time of forming the predetermined pattern in each of the plurality of second regions on the second substrate, to change a position of the predetermined pattern in each of the plurality of second regions in a direction of being closer to a center of the second substrate for a first direction and to change the position of the predetermined pattern in a direction of being farther from the center of the second substrate for a second direction.

Abstract: According to one embodiment, a semiconductor device includes a first chip, and a second chip bonded to the first chip. The first chip includes: a substrate; a transistor provided on the substrate; a plurality of first wirings provided above the transistor; and a plurality of first pads provided above the first wirings. The second chip includes: a plurality of second pads coupled to the plurality of first pads, respectively; a plurality of second wirings provided above the second pads; and a memory cell array provided above the second wirings. The first wiring, the first pad, the second pad, and the second wiring are coupled to one another in series to form a first pattern.

Abstract: A data latch circuit includes a first transistor of a first conductivity type and a second transistor of the first conductivity type, and a third transistor of a second conductivity type and a fourth transistor of the second conductivity type. The third and fourth transistors are controlled to perform a first control operation to store data in the data latch circuit and to perform a second control operation to read the stored data.

Abstract: According to one embodiment, in a semiconductor memory device, a gate electrode of a first PMOS transistor and a gate electrode of a first NMOS transistor are commonly connected, and a first contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with an isolation portion when viewed in a third direction perpendicular to a first direction and a second direction. A gate electrode of a second PMOS transistor and a gate electrode of a second NMOS transistor are commonly connected, and a second contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with the isolation portion when viewed in the third direction.

Abstract: A semiconductor storage device includes first conductive layers stacked in a first direction and extend in a second direction; second conductive layers stacked in the first direction and extend in the second direction; third conductive layers that are electrically connected to the first conductive layers and the second conductive layers and stacked in the first direction; a first insulating layer and a second insulating layer sandwich the first conductive layer; a third insulating layer and a fourth insulating layer sandwich the second conductive layer; first pillars arranged in the second direction in the first insulating layer with a first distance; and second pillars arranged in the second direction in the second insulating layer with the first distance. Each of the second pillars is displaced from a corresponding one of the first pillars by a second distance that is shorter than a half of the first distance in the second direction.

Abstract: According to one embodiment, a semiconductor memory device comprises a substrate, a first conductive layer, and a second conductive layer arranged in this order in a first direction and separated from each other, a first semiconductor film extending in the first direction, intersecting the first conductive layer, and being in contact with the second conductive layer, and a first charge storage film arranged between the first semiconductor film and the first conductive layer, and being in contact with the second conductive layer, wherein the first semiconductor film includes a first portion formed of an n-type semiconductor at approximately a same height as the first conductive layer.

Abstract: In one embodiment, a semiconductor device includes a substrate, transistors on the substrate, and a stacked film provided above the transistors, including electrode layers separated from each other in a first direction, and including first, second and third regions. The device further includes plugs provided to the electrode layers in the first region, a first columnar portion in the second region, and a second columnar portion in the third region. At least one electrode layer among the electrode layers includes a first portion in the first region, a second portion in the second region, and a third portion in the third region, and is a continuous film from the second portion to the third portion via the first portion. The transistors include first, second and third transistors provided right under the first, second and third regions and electrically connected to first, second and third plugs among the plugs, respectively.