Patents by Inventor Keith Edward Fogel

Keith Edward Fogel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9404942
    Abstract: Coaxial probe structures include a plurality of discrete insulated elongated electrical conductors projecting from a support surface which are useful as probes for testing of electrical interconnections to electronic devices, such as integrated circuit devices and other electronic components and particularly for testing of integrated circuit devices with rigid interconnection pads and multi-chip module packages with high density interconnection pads. Coaxial probe structures are fabricated by the methods described providing a high density coaxial probe.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Yun-Hsin Liao, Daniel Peter Morris, Da-Yuan Shih
  • Publication number: 20140191775
    Abstract: The present invention is directed to structures having a plurality of discrete insulated elongated electrical conductors projecting from a support surface which are useful as probes for testing of electrical interconnections to electronic devices, such as integrated circuit devices and other electronic components and particularly for testing of integrated circuit devices with rigid interconnection pads and multi-chip module packages with high density interconnection pads and the apparatus for use thereof and to methods of fabrication thereof. Coaxial probe structures are fabricated by the methods described providing a high density coaxial probe.
    Type: Application
    Filed: February 7, 2014
    Publication date: July 10, 2014
    Applicant: International Business Machines Corporation
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Yun-Hsin Liao, Daniel Peter Morris, Da-Yuan Shih
  • Patent number: 8754666
    Abstract: Structures having a plurality of discrete insulated elongated electrical conductors projecting from a support surface which are useful as probes for testing of electrical interconnections to electronic devices, such as integrated circuit devices and other electronic components and particularly for testing of integrated circuit devices with rigid interconnection pads and multi-chip module packages with high density interconnection pads and the apparatus for use thereof and to methods of fabrication thereof. Coaxial probe structures are fabricated by the methods described providing a high density coaxial probe.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Yun-Hsin Liao, Daniel Peter Morris, Da-Yuan Shih
  • Patent number: 8491772
    Abstract: The present invention is directed to structures having a plurality of discrete insulated elongated electrical conductors projecting from a support surface which are useful as probes for testing of electrical interconnections to electronic devices, such as integrated circuit devices and other electronic components and particularly for testing of integrated circuit devices with rigid interconnection pads and multi-chip module packages with high density interconnection pads and the apparatus for use thereof and to methods of fabrication thereof. Coaxial probe structures are fabricated by the methods described providing a high density coaxial probe.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Yun-Hsin Liao, Daniel Peter Morris, Da-Yuan Shih
  • Patent number: 8486250
    Abstract: The present invention is directed to structures having a plurality of discrete insulated elongated electrical conductors projecting from a support surface which are useful as probes for testing of electrical interconnections to electronic devices, such as integrated circuit devices and other electronic components and particularly for testing of integrated circuit devices with rigid interconnection pads and multi-chip module packages with high density interconnection pads and the apparatus for use thereof and to methods of fabrication thereof. Coaxial probe structures are fabricated by the methods described providing a high density coaxial probe.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Yun-Hsin Liao, Daniel Peter Morris, Da-Yuan Shih
  • Patent number: 7960263
    Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Keith Edward Fogel, Katherine L. Saenger, Chun-Yung Sung, Haizhou Yin
  • Publication number: 20100203708
    Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches.
    Type: Application
    Filed: April 26, 2010
    Publication date: August 12, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith Edward Fogel, Katherine L. Saenger, Chun-Yung Sung, Haizhou Yin
  • Publication number: 20100052715
    Abstract: The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires.
    Type: Application
    Filed: August 27, 2009
    Publication date: March 4, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George Frederick Walker
  • Publication number: 20100045321
    Abstract: The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires.
    Type: Application
    Filed: August 27, 2009
    Publication date: February 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George Frederick Walker
  • Publication number: 20100045320
    Abstract: The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires.
    Type: Application
    Filed: August 27, 2009
    Publication date: February 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George Frederick Walker
  • Publication number: 20100045318
    Abstract: The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires.
    Type: Application
    Filed: August 27, 2009
    Publication date: February 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George Frederick Walker
  • Publication number: 20100045324
    Abstract: The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires.
    Type: Application
    Filed: August 27, 2009
    Publication date: February 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George Frederick Walker
  • Publication number: 20100045266
    Abstract: The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires.
    Type: Application
    Filed: August 27, 2009
    Publication date: February 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George Frederick Walker
  • Publication number: 20100045317
    Abstract: The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires.
    Type: Application
    Filed: August 27, 2009
    Publication date: February 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George Frederick Walker
  • Publication number: 20090315579
    Abstract: The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires.
    Type: Application
    Filed: August 27, 2009
    Publication date: December 24, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George Frederick Walker
  • Publication number: 20090308756
    Abstract: The present invention is directed to structures having a plurality of discrete insulated elongated electrical conductors projecting from a support surface which are useful as probes for testing of electrical interconnections to electronic devices, such as integrated circuit devices and other electronic components and particularly for testing of integrated circuit devices with rigid interconnection pads and multi-chip module packages with high density interconnection pads and the apparatus for use thereof and to methods of fabrication thereof. Coaxial probe structures are fabricated by the methods described providing a high density coaxial probe.
    Type: Application
    Filed: August 21, 2009
    Publication date: December 17, 2009
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Yun-Hsin Liao, Daniel Peter Morris, Da-Yuan Shih
  • Publication number: 20090233079
    Abstract: Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein. In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a three dimensional integrated structure is provided.
    Type: Application
    Filed: May 27, 2009
    Publication date: September 17, 2009
    Applicant: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Keith Edward Fogel, Bruce Kenneth Furman, Sampath Purushothaman, Devendra K. Sadana, Anna Wanda Topol
  • Publication number: 20090189288
    Abstract: A method is described having the steps of providing a surface having a plurality of wire bondable locations; wire bonding a wire to each of the wire bondable locations using a wire capillary tool; controlling the position of the capillary tool with respect to the substrate; after forming a wire bond of the wire to the wire bondable location moving the capillary tool relative to the surface as the capillary tool is moved away from the surface to form a wire having a predetermined shape.
    Type: Application
    Filed: January 22, 2009
    Publication date: July 30, 2009
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Da-Yuan Shih
  • Patent number: 7550369
    Abstract: The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: June 23, 2009
    Assignee: International Business Machines Corporation
    Inventors: Joel Pereira de Souza, Keith Edward Fogel, John Albrecht Ott, Devendra Kumar Sadana, Katherine Lynn Saenger
  • Patent number: 7538565
    Abstract: A high density test probe which provides an apparatus for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: May 26, 2009
    Assignee: International Business Machines Corporation
    Inventors: Brian Samuel Beaman, Keith Edward Fogel, Paul Alfred Lauro, Maurice Heathcote Norcott, Da-Yuan Shih, George Frederick Walker