Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for providing a hermetic seal for a layer of transistors with metal on both sides that are on a substrate. The layer of transistors may be within a die or within a portion of a die. The hermetic seal may include a hermetic layer on one side of the layer of transistors and a hermetic layer on the opposite side of the transistors. In embodiments, one or more metal walls may be constructed through the transistor layer, with metal rings placed around either side of the layer of transistors and hermetically coupling with the two hermetic layers. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for a barrier that surrounds one or more dies which are electrically coupled with one or more electrical connections on a wafer. The barrier may be a hermetic barrier that is formed on a wafer prior to singulation to prevent moisture intrusion from a side of the wafer that may compromise the one or more electrical connections. Other embodiments may be described and/or claimed.

Abstract: The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed regions; forming source/drain extensions adjacent to both sides of the gate with a dopant; and performing an anneal to activate the dopant.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region.

Abstract: An apparatus comprising a semiconductor substrate; a conductively doped source or drain (source/drain) region at the surface of the substrate; a raised semiconductor layer deposited over the source/drain region to form a raised source/drain region; a via formed in the raised source/drain region having substantially vertical sidewalls reaching partly or substantially to the source/drain region; and a metal contact filling the via.

Abstract: The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed regions; forming source/drain extensions adjacent to both sides of the gate with a dopant; and performing an anneal to activate the dopant.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a (100) plane to form at least one (111) region in the recessed source/drain region.

Abstract: Carbon may be implanted into a p-type silicon channel to form a carbon region in an n-type metal oxide semiconductor (NMOS) transistor. After an annealing process, the implanted carbon may diffuse from the channel into an interface of a gate dielectric layer and the channel. The diffusion may cause an increase in fixed charge at the silicon surface. Thus, the threshold voltage of the NMOS transistor may be reduced.

Abstract: Optimal strain in the channel region of a PMOS transistor is provided by silicon alloy material in the junction regions of the device in a non-planar relationship with the surface of the substrate. The silicon alloy material, the dimensions of the silicon alloy material, as well as the non-planar relationship of the silicon alloy material with the surface of the substrate are selected so that the difference between the lattice spacing of the silicon alloy material and of the substrate causes strains in the silicon alloy material below the substrate surface, as well as above the substrate surface, to affect an optimal silicon alloy induced strain in the substrate channel. In addition, the non-planar relationship may be selected so that any strains caused by different lattice spaced layers formed over the silicon alloy material have a reduced effect on the strain in the channel region.