Patents by Inventor Kelwin King Wai Ko

Kelwin King Wai Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7060564
    Abstract: A method of fabricating a memory device having a core region of double-bit memory cells and a periphery region of logic circuitry includes forming a dielectric stack over the core and periphery areas of a semiconductor substrate and removing the dielectric stack from the periphery region. A gate dielectric is formed over the periphery area, followed by a first conductive layer over the core and periphery areas. After the formation and thermal processing of the gate dielectric, bitlines, which serve as source and drain regions, are implanted into the core area. Formation of the bitlines after the gate dielectric layer reduces lateral bitline diffusion and reduces short channel effects.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: June 13, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Inkuk Kang, Hiroyuki Kinoshita, Weidong Qian, Kelwin King Wai Ko, Yu Sun
  • Patent number: 6613657
    Abstract: Device leakage due to spacer undercutting is remedied by depositing a BPSG, SA-CVD oxide liner and flowing it into the undercut regions, followed by gap filling with a P-doped HDP oxide layer. Embodiments include depositing a BPSG, SA-CVD oxide liner containing 4 to 6 wt.% boron, at a thickness of 1,000 Å to 1,800 Å, over closely spaced apart non-volatile transistors and heating during or subsequent to deposition to flow the BPSG, SA-CVD oxide liner into the undercut regions of the sidewall spacers of the gate stacks. Gap filling is then completed by depositing the layer of P-doped HDP at a thickness of 6,000 Å to 10,000 Å.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: September 2, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Dawn Hopper, Wenmei Li, Kelwin King Wai Ko, Kuo-Tung Chang, Tyagamohan Gottipati
  • Publication number: 20010006847
    Abstract: The present invention provides a method for providing an interconnect in a flash memory device. A first embodiment includes forming at least one contact hole in a peripheral area of the device; bombarding a bottom of the at least one contact hole with ions, where the ions break down undesired oxide residing at the bottom of the at least one contact hole; depositing a barrier metal layer into the at least one contact hole, where the barrier metal layer breaks down remaining undesired oxide at the bottom of the at least one contact hole, and where bombarding with the ions and the depositing of the barrier metal layer minimize an undesired widening of the at least one contact hole; and depositing a contact material into the at least one contact hole. With the first embodiment, both the ions and the titanium break down the undesired oxide while neither breaks down the desired oxide at the sides of the contact hole to a significant degree.
    Type: Application
    Filed: February 1, 2001
    Publication date: July 5, 2001
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John JianShi Wang, Kent Kuohua Chang, Hao Fang, Kelwin King Wai Ko, Mark S. Chang, Angela T. Hui