Patents by Inventor Ken Elliott
Ken Elliott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8771406Abstract: A transport tank with high capacity gas scrubbing includes a vertically extending interior wall horizontally dividing the transport tank into a gas scrubbing chamber and a fluid storage chamber. A floor grate is supported within the gas scrubbing chamber at vertically spaced distance from a bottom of the transport tank and defines a gas distribution space between the floor grate and the tank bottom. A gas distribution pipe is disposed within and longitudinally extends the gas distribution space. A gas inlet is fluidically connected to the gas distribution pipe and passes through an exterior wall of the transport tank. A gas scrubbing is material disposed within the gas scrubbing chamber above the floor grate. And a gas outlet is fluidically connected to the gas scrubbing chamber for venting scrubbed gases.Type: GrantFiled: February 21, 2013Date of Patent: July 8, 2014Inventors: Ken Elliott, Sonya Elliott
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Patent number: 8242538Abstract: A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.Type: GrantFiled: May 11, 2011Date of Patent: August 14, 2012Assignee: HRL Laboratories, LLCInventors: Peter Deelman, Ken Elliott, David Chow
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Patent number: 8193611Abstract: Material layer structures that have high mobility, a high conduction band barrier and materials that can be implanted to enable higher performance FET device. The structures contain a quantum well layer disposed between two barriers and disposed above a buffer layer and a substrate.Type: GrantFiled: December 19, 2006Date of Patent: June 5, 2012Assignee: HRL Laboratories, LLCInventors: Rajesh Rajavel, Ken Elliott, David Chow
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Patent number: 7968435Abstract: A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.Type: GrantFiled: June 24, 2009Date of Patent: June 28, 2011Assignee: HRL Laboratories, LLCInventors: Peter Deelman, Ken Elliott, David Chow
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Patent number: 7667515Abstract: Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and second transistor differential pairs 218 and 220, receives an analog input signal 202 without a delay as well as a delayed input signal 210 produced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signal 232 and a second control signal 238, effectively altering the mixing of the undelayed input signal 208 and the delayed input signal 210 to generate a delayed output signal 214 with a time or phase delay substantially equal to the temporal delay represented by the digital signal input 204. The time delay generator exhibits reduced phase noise and a linear time delay response.Type: GrantFiled: May 31, 2008Date of Patent: February 23, 2010Assignee: HRL Laboratories, LLCInventors: Ken Elliott, Susan Morton, Mark Rodwell
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Patent number: 7598158Abstract: A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.Type: GrantFiled: June 5, 2006Date of Patent: October 6, 2009Assignee: HRL Laboratories, LLCInventors: Peter Deelman, Ken Elliott, David Chow
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Patent number: 7514708Abstract: A sub-micron, on the order of 80-nanometer diameter, resonant tunneling diode having a peak-to-valley ratio of approximately 5.1 to 1, and a method for its manufacture. The invention is unique in that its performance characteristics are unmatched in comparably sized resonant tunneling diodes. Further, the polyimide passivation and planarization methodology provides unexpected processing advantages with respect to application in the fabrication of resonant tunneling diodes. The invention includes a substrate 100 that serves as a foundation for bottom contact layers 102 and a polyimide 700 coating. An ohmic metal contact 300 and emitter metal contact 400 protrude above the polyimide 700 coating exposing the ohmic metal contact 300 and emitter metal contact 400. The contacts are capped with an etch-resistant coating 710 thus allowing for the polyimide etch, and other etching processes without adversely affecting the contacts.Type: GrantFiled: April 22, 2003Date of Patent: April 7, 2009Assignee: HRL Laboratories, LLCInventors: Stephen Thomas, III, Ken Elliott, David H. Chow
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Patent number: 7446584Abstract: Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and second transistor differential pairs 218 and 220, receives an analog input signal 202 without a delay as well as a delayed input signal 210 produced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signal 232 and a second control signal 238, effectively altering the mixing of the undelayed input signal 208 and the delayed input signal 210 to generate a delayed output signal 214 with a time or phase delay substantially equal to the temporal delay represented by the digital signal input 204. The time delay generator exhibits reduced phase noise and a linear time delay response.Type: GrantFiled: September 25, 2002Date of Patent: November 4, 2008Assignee: HRL Laboratories, LLCInventors: Ken Elliott, Susan Morton, Mark Rodwell
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Publication number: 20040056698Abstract: Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and second transistor differential pairs 218 and 220, receives an analog input signal 202 without a delay as well as a delayed input signal 210 produced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signal 232 and a second control signal 238, effectively altering the mixing of the undelayed input signal 208 and the delayed input signal 210 to generate a delayed output signal 214 with a time or phase delay substantially equal to the temporal delay represented by the digital signal input 204. The time delay generator exhibits reduced phase noise and a linear time delay response.Type: ApplicationFiled: September 25, 2002Publication date: March 25, 2004Inventors: Ken Elliott, Susan Morton, Mark Rodwell
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Publication number: 20030230759Abstract: A sub-micron, on the order of 80-nanometer diameter, resonant tunneling diode having a peak-to-valley ratio of approximately 5.1 to 1, and a method for its manufacture. The invention is unique in that its performance characteristics are unmatched in comparably sized resonant tunneling diodes. Further, the polyimide passivation and planarization methodology provides unexpected processing advantages with respect to application in the fabrication of resonant tunneling diodes. The invention includes a substrate 100 that serves as a foundation for bottom contact layers 102 and a polyimide 700 coating. An ohmic metal contact 300 and emitter metal contact 400 protrude above the polyimide 700 coating exposing the ohmic metal contact 300 and emitter metal contact 400. The contacts are capped with an etch-resistant coating 710 thus allowing for the polyimide etch, and other etching processes without adversely affecting the contacts.Type: ApplicationFiled: April 22, 2003Publication date: December 18, 2003Inventors: Stephen Thomas, Ken Elliott, David H. Chow
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Publication number: 20030034499Abstract: A sub-micron, on the order of 80-nanometer diameter, resonant tunneling diode having a peak-to-valley ratio of approximately 5.1 to 1, and a method for its manufacture. The invention is unique in that its performance characteristics are unmatched in comparably sized resonant tunneling diodes. Further, the polyamide passivation and planerization methodology provides unexpected processing advantages with respect to application in the fabrication of resonant tunneling diodes. The invention includes a substrate 706 that serves as a foundation for bottom contact layers 708 and a polyamide 700 coating. An ohmic metal contact 702 and emitter metal contact 704 protrude above the polyamide 700 coating exposing the ohmic metal contact 702 and emitter metal contact 704. The contacts are capped with an etch resistant coating 710 thus allowing for the polyamide etch, and other etching processes without adversely affecting the contacts.Type: ApplicationFiled: August 7, 2001Publication date: February 20, 2003Inventors: Stephen Thomas, Ken Elliott, Dave Chow