Patents by Inventor Ken Inoue

Ken Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7357980
    Abstract: A nonmagnetic powder, used for the nonmagnetic layer of a coated type magnetic recording medium having a multilayer structure, has good dispersibility in the binder in which it is dispersed to prepare a coating material that is applied to the nonmagnetic layer. The nonmagnetic powder has an iron compound as its principal component and exhibits a maximum pore volume value in a pore diameter range of 0.01 ?m to 0.05 ?m within a pore diameter range of 0.0018 ?m to 0.1 ?m in which the relationship between pore diameter and pore volume is calculated by a mercury injection method. The nonmagnetic powder exhibits a cumulative pore volume value in a pore diameter range of 0.0018 ?m to 0.01 ?m that is not more than 30% of the cumulative pore volume value in the pore diameter range of 0.0018 ?m to 0.1 ?m.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: April 15, 2008
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Shinichi Konno, Kenichi Inoue, Toshihiko Ueyama, Ken Inoue
  • Patent number: 7357997
    Abstract: A powder for an underlayer of a coating-type magnetic recording medium comprises acicular iron oxide particles having an average major axis length in the range of 20-200 nm, has a specific surface area measured by the BET method of 30-100 m2/g and has a powder pH of not greater than 7. The underlayer powder preferably contains 0.1-5.0 wt. % of P and optionally contains an amount of R (where R represents one or more rare earth elements, defined as including Y) such that R/Fe expressed in atomic percentage (at. %) is 0.1-10 at. %. The iron oxide powder enhances the properties required of a powder for forming the underlayer of a multi-layer structure coating-type magnetic recording tape, most notably the surface smoothness and strength of the tape.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: April 15, 2008
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Kazuyuki Matsumoto, Kenichi Inoue, Ken Inoue
  • Publication number: 20070212831
    Abstract: The short circuit between the bit line and thee cell contact can be prevented without considerably increasing the number of the manufacturing processes. The bit line 6 electrically coupled to the cell contact 9 is formed of the material, which is same as the material of cell contact 9. In the process for forming the bit line 6 on the cell contact interlayer film 8 by etching, the etching for creating an upper surface of the cell contact 9 that is not coupled to the bit line 6 being lower than an upper surface of the cell contact 9 that is coupled to the bit line 6. Further, after the formation of the bit line 6, the barrier metal layer 5 formed on the lower surface of the bit line 6 is selectively etched.
    Type: Application
    Filed: May 9, 2007
    Publication date: September 13, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tomoko Inoue, Ken Inoue
  • Patent number: 7247904
    Abstract: A circuit provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process. A hard mask is formed on the bit line upper surface and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film without the SAC structure is etched off except where bit line is formed. A direct nitride film is formed on the entire top and side surface of the bit line so as to cover the bit line in one processing step. Since the upper and side nitride film thicknesses are substantially the same, the height of the bit line can be reduced, enabling further miniaturization. In addition, since the sidewall nitride film is formed without an etch back process, it can more easily be formed with a constant film thickness.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: July 24, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Tomoko Inoue, Ken Inoue
  • Patent number: 7247903
    Abstract: A semiconductor memory device having a transistor formed on a semiconductor substrate and a capacitor formed on the upper layer of the transistor and electrically connected to the transistor, includes: a cell contact which is formed on a first interlayer insulation film covering the transistor and is electrically connected to the transistor; a bit contact which is formed on a second interlayer insulation film provided on the first interlayer insulation film and is electrically connected to the cell contact; a bit line which is formed on the second interlayer insulation film and is connected to the bit contact; a capacitor which is formed on a third interlayer insulation film covering the bit line; a capacitor contact which is formed through the third and second interlayer insulation film and makes a connection between the capacitor and the cell contact; and a side wall which has an etching selectivity with the second and third interlayer insulation films formed on the surface of the bit line.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: July 24, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Ken Inoue, Shintaro Arai
  • Patent number: 7238980
    Abstract: The short circuit between the bit line and thee cell contact can be prevented without considerably increasing the number of the manufacturing processes. The bit line 6 electrically coupled to the cell contact 9 is formed of the material, which is same as the material of cell contact 9. In the process for forming the bit line 6 on the cell contact interlayer film 8 by etching, the etching for creating an upper surface of the cell contact 9 that is not coupled to the bit line 6 being lower than an upper surface of the cell contact 9 that is coupled to the bit line 6. Further, after the formation of the bit line 6, the barrier metal layer 5 formed on the lower surface of the bit line 6 is selectively etched.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: July 3, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Tomoko Inoue, Ken Inoue
  • Patent number: 7238438
    Abstract: A powder for an underlayer of a coating-type magnetic recording medium, which powder comprises flat-acicular iron oxide particles having an average major axis length of 20–200 nm, a short axis cross-section taken perpendicularly to the long axis that has a long width and a short width, and a short axis cross-section ratio defined as the ratio of the long width to the short width that is greater than 1.3 and substantially uniform in the long axis direction, the powder having a specific surface area measured by the BET method of 30–100 m2/g. The underlayer powder preferably contains 0.1–5.0 wt % of P and, optionally, an amount of R(R representing one or more rare earth elements, defined as including Y) such that R/Fe expressed in atomic percentage (at. %) is 0.1–10 at. %.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: July 3, 2007
    Assignee: Dowa Mining Co., Ltd.
    Inventors: Kazuyuki Matsumoto, Kenichi Inoue, Ken Inoue
  • Publication number: 20070009737
    Abstract: Non-magnetic powder of particles for non-magnetic lower layer applications is provided that enables a multilayer coating type magnetic recording medium having good surface smoothness to be obtained. The particles are iron compound particles having a long axis with a standard geometrical deviation, as obtained from a transmission electron microscope image, that is greater than 1.5, and a short axis with a standard geometrical deviation, as obtained from a TEM image, that is greater than 1.35. The iron compound particles may be hematite or iron oxyhydroxide.
    Type: Application
    Filed: June 23, 2006
    Publication date: January 11, 2007
    Inventors: Shinichi Konno, Toshihiko Ueyama, Kenichi Inoue, Takayuki Yoshida, Ken Inoue
  • Patent number: 7159640
    Abstract: A casting member comprising hot-die steel or high-speed steel as base material and having coating layers at least on its working plane, wherein the outermost layer among the coating layers consists essentially of at least one nitride, oxinitride or carnonitride composed mainly of V, and another coating layer comprising at least one nitride, oxinitride or carnonitride composed mainly of Cr is formed as a layer just above the base material. If necessary, an intermediate layer comprising at least one nitride, oxinitride or carnonitride composed mainly of V and Cr may be formed as a coating layer on the boundary surface between the outermost layer and the layer just above the base material. The thickness of the outermost layer is preferably 0.5 to 5.0 ?m, the thickness of the layer just above the base material is preferably 0.5 to 3.0 ?m, and the thickness of the intermediate layer is preferably 1.0 ?m or less.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: January 9, 2007
    Assignee: Hitachi Metals, Ltd.
    Inventors: Kenichi Inoue, Ken Inoue
  • Publication number: 20060234081
    Abstract: It is an object of the present invention to provide a multi-layer coating having excellent adhesion and sliding properties, which contains a hard layer having a main component of a nitride and/or carbonitride containing one or more elements selected from the group consisting of Ti, V, Zr, Cr, Nb, Si, Al and B and a lubricating layer consisting of a metal element and molybdenum disulfide on the hard layer wherein the lubricating layer has a graded composition in which the metal element has a decreasing content from the hard layer side towards the surface and the molybdenum disulfide has an increasing content, and wherein the lubricating layer has a maximum oxygen concentration of no greater than 25 atom %.
    Type: Application
    Filed: March 15, 2006
    Publication date: October 19, 2006
    Inventors: Ken Inoue, Kenichi Inoue
  • Patent number: 7105882
    Abstract: The present invention provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process, in which a hard mask is formed on the upper surface of the bit line and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film of the conventional semiconductor device which does not have the SAC structure is etched off except the portion where bit line is formed, and then direct nitride film is formed on the entire surface of the top surface and the side surface of the bit line so as to cover the bit line in a same processing step. Since the film thickness of the nitride film disposed on the upper surface of the bit line is designed to be substantially the same as that disposed on the side surface of the nitride film, the height of the bit line itself can be reduced, and thus a further miniaturization becomes possible.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: September 12, 2006
    Assignee: NEC Electronics Corporation
    Inventors: Tomoko Inoue, Ken Inoue
  • Patent number: 7102628
    Abstract: A computing system includes a handwriting input device and a computing device, the handwriting input device including an electronic pen input device having a first tip that emits a signal having a first characteristic and second tip that emits a signal having second characteristic; a detector for detecting the characteristic of the emitted signal; and a controller, interfaced with the computing device, for selectively interpreting the emitted signal as handwriting or as control information for the computing device based on the detected characteristic of the emitted signal.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: September 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Scott LeKuch, Ken Inoue, Dan Peter Dumarot, Mary R. Seminara, Sreenivasulu Kesavarapu, John Peter Karidis
  • Publication number: 20060192236
    Abstract: The present invention provides a semiconductor device comprising: a semiconductor substrate having a DRAM portion and a Logic portion; a first transistor in said DRAM portion; a second transistor in said Logic portion; a first insulating layer covering said DRAM portion and said Logic portion; a first contact plug formed in said first insulating layer in electrically contact with said first transistor in said DRAM portion; a first bit line for said DRAM portion formed on said first insulating layer in electrically contact with said first contact plug; a nitride film formed in contact with said first insulating layer to cover said DRAM portion and said Logic portion, wherein said first bit line locating between said first insulating layer and said nitride film.
    Type: Application
    Filed: February 6, 2006
    Publication date: August 31, 2006
    Inventors: Tomoko Inoue, Ken Inoue
  • Patent number: 7098880
    Abstract: The invention provides an electrooptic device that can include a first substrate on which pixel electrodes, first thin film transistors electrically connected to the pixel electrodes, and scanning lines and data lines electrically connected to the first thin film transistors are formed, a second substrate opposing the first substrate and having a common electrode, and an electrooptic substance held between the first substrate and the second substrate. The electrooptical device can further include a switching element for discharging in capacitors constituted by the pixel electrodes on the first substrate, the electrooptic substance, and the common electrode on the second substrate. The invention makes it possible to remove charges from inside the electrooptic device.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: August 29, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Ken Inoue, Toshiyuki Hirase, Sadasumi Uchiyama
  • Publication number: 20060186448
    Abstract: A circuit provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process. A hard mask is formed on the bit line upper surface and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film without the SAC structure is etched off except where bit line is formed. A direct nitride film is formed on the entire top and side surface of the bit line so as to cover the bit line in one processing step. Since the upper and side nitride film thicknesses are substantially the same, the height of the bit line can be reduced, enabling further miniaturization. In addition, since the sidewall nitride film is formed without an etch back process, it can more easily be formed with a constant film thickness.
    Type: Application
    Filed: April 24, 2006
    Publication date: August 24, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tomoko Inoue, Ken Inoue
  • Publication number: 20060166040
    Abstract: An underlayer powder for a coating-type double-layer magnetic recording medium is a powder composed of acicular nonmagnetic iron oxide particles whose average major axis length of the particles is 20-200 nm, and specific surface area calculated by BET method is 30-100 m2/g, which has a phosphorus content in the particulate powder of 0.1-5 wt %, and soluble phosphorus compound of not greater than 100 ppm based on P, and which preferably has a powder pH of less than 8, a soluble sodium content of not greater than 100 ppm based on Na and soluble sulfate of not greater than 100 ppm based on SO4.
    Type: Application
    Filed: July 1, 2004
    Publication date: July 27, 2006
    Inventors: Shinichi Konno, Kenichi Inoue, Ken Inoue, Hiroshi Iihoshi, Toshihiko Ueyamaa
  • Publication number: 20060040141
    Abstract: A nonmagnetic powder, used for the nonmagnetic layer of a coated type magnetic recording medium having a multilayer structure, has good dispersibility in the binder in which it is dispersed to prepare a coating material that is applied to the nonmagnetic layer. The nonmagnetic powder has an iron compound as its principal component and exhibits a maximum pore volume value in a pore diameter range of 0.01 ?m to 0.05 ?m within a pore diameter range of 0.0018 ?m to 0.1 ?m in which the relationship between pore diameter and pore volume is calculated by a mercury injection method. The nonmagnetic powder exhibits a cumulative pore volume value in a pore diameter range of 0.0018 ?m to 0.01 ?m that is not more than 30% of the cumulative pore volume value in the pore diameter range of 0.0018 ?m to 0.1 ?m.
    Type: Application
    Filed: August 19, 2005
    Publication date: February 23, 2006
    Inventors: Shinichi Konno, Kenichi Inoue, Toshihiko Ueyama, Ken Inoue
  • Publication number: 20060032602
    Abstract: A casting member comprising hot-die steel or high-speed steel as base material and having coating layers at least on its working plane, wherein the outermost layer among the coating layers consists essentially of at least one nitride, oxinitride or carnonitride composed mainly of V, and another coating layer comprising at least one nitride, oxinitride or carnonitride composed mainly of Cr is formed as a layer just above the base material. If necessary, an intermediate layer comprising at least one nitride, oxinitride or carnonitride composed mainly of V and Cr may be formed as a coating layer on the boundary surface between the outermost layer and the layer just above the base material. The thickness of the outermost layer is preferably 0.5 to 5.0 ?m, the thickness of the layer just above the base material is preferably 0.5 to 3.0 ?m, and the thickness of the intermediate layer is preferably 1.0 ?m or less.
    Type: Application
    Filed: August 8, 2005
    Publication date: February 16, 2006
    Inventors: Kenichi Inoue, Ken Inoue
  • Patent number: 6995413
    Abstract: A semiconductor memory device having a transistor and a capacitor electrically connected to the transistor, the semiconductor memory device comprising: a first interlayer insulation film covering said transistor; a metallic cell contact passing through said first interlayer insulation film, said cell contact being electrically connected to said transistor; at least one interlayer insulation film located above said first interlayer insulation film; a capacitor located above said first interlayer insulation film; and a capacitor contact passing through said at least one interlayer insulation film, said capacitor contact electrically connecting said capacitor with said cell contact.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: February 7, 2006
    Assignee: NEC Electronics Corporation
    Inventors: Ken Inoue, Shintaro Arai
  • Publication number: 20060017090
    Abstract: A semiconductor device includes a cylinder-shaped capacitor. The capacitor includes a second insulating layer formed with a recessed portion formed on a semiconductor substrate, a cylinder shaped lower electrode formed in the recessed portion, a capacitance layer formed on the lower electrode, and an upper electrode formed on the capacitance layer. The upper electrode includes a first metal layer formed by PVD and a second metal layer formed thereafter by CVD, and the cylinder sidewall of the first metal layer has a thickness of 2 nm or less.
    Type: Application
    Filed: July 14, 2005
    Publication date: January 26, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Naomi Fukumaki, Yoshitake Kato, Ken Inoue