Ken Pomaranski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: An example memory error ranking system is provided. The system may include an error detector logic that detects memory errors and a ranking logic that ranks the quality of a memory location based on memory errors detected by the error detector logic.
Abstract: One embodiment disclosed relates to a method for persistently tracking volatile memory faults. A memory error is detected in relation to at least one dynamic random access memory (DRAM) unit on a particular memory module. An entry pertaining to the memory error is written in non-volatile memory of a fault storage unit on that particular memory module. Another embodiment disclosed relates to a memory module that persistently tracks volatile memory faults. The memory module includes a plurality of dynamic random access memories (DRAMs) and a fault storage unit. The fault storage unit includes non-volatile memory configured to store entries pertaining to faults in the plurality of DRAMs on that memory module.
Abstract: One embodiment disclosed relates to a method of visually locating a memory module. An electronic communication is received by circuitry on the memory module to be visually located. A beacon state in the memory module is activated due to receipt of the electronic communication. A beacon device on the memory module is electronically turned on when the beacon state is activated to draw attention to that memory module. Another embodiment disclosed relates to an apparatus to visually locate a memory module in a memory system with a plurality of memory modules. The apparatus includes a system board, a plurality of memory modules, and an LED unit on a memory module. The beacon unit includes a beacon device and control circuitry for turning on the beacon device when an electronic communication to turn on the beacon device is received by that memory module.
Abstract: One embodiment disclosed pertains to a printed circuit assembly (PCA) with built-in circuitry to test integrated circuit (IC) connector loading. The PCA includes at least the IC connector to be tested, an indicator circuit, and a power circuit. The IC connector is configured to interconnect to a packaged IC. The indicator circuit is coupled to the IC connector. Proper seating of the packaged IC in the IC connector is determined and indicated by the indicator circuit. The power circuit provides power to the indicator circuit.
June 12, 2003
February 3, 2005
Dale Shidla, Andrew Barr, Ken Pomaranski
Abstract: One embodiment disclosed relates to a microprocessor for targeted fault-tolerant computing. The microprocessor's decode circuitry is configured to decode a fault-tolerant version of an instruction and a non-fault-tolerant version of the instruction distinctly from each other. The microprocessor's execution circuitry is configured to execute the fault-tolerant version of the instruction with redundancy checking and to execute the non-fault-tolerant version of the instruction without redundancy checking.
July 18, 2003
January 20, 2005
Ken Pomaranski, Andrew Barr, Dale Shidla