Patents by Inventor Ken Wakita
Ken Wakita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220121154Abstract: A watch component having an oxide film formed by oxidizing a base material containing iron as a main component, an average film thickness of the oxide film is from 70 nm to 145 nm, and a variation in film thickness of the oxide film is equal to or less than 35%.Type: ApplicationFiled: October 19, 2021Publication date: April 21, 2022Inventors: Takeshi SAKAMOTO, Kazunori HOSHINO, Takahiro SEKI, Ken WAKITA
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Patent number: 8896775Abstract: An electro-optical device includes a pixel electrode provided on a substrate, a transistor provided between the substrate and the pixel electrode, a first capacitor electrode provided between the pixel electrode and the transistor, and be electrically connected to the pixel electrode and the transistor, a second capacitor electrode provided between the pixel electrode and the first capacitor electrode, be located so as to be opposite the first capacitor electrode via a capacitor insulating film, and be supplied with a predetermined electric potential, and a light-shielding film provided between the pixel electrode and the second capacitor electrode, be located so as to be at least partially overlapped by the transistor, and be electrically connected to the second capacitor electrode via a contact hole formed in an insulating film disposed between the second capacitor electrode and the light-shielding film.Type: GrantFiled: March 8, 2011Date of Patent: November 25, 2014Assignee: Seiko Epson CorporationInventors: Minoru Moriwaki, Masahiro Yasukawa, Ken Wakita
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Publication number: 20110222008Abstract: An electro-optical device includes a pixel electrode provided on a substrate, a transistor provided between the substrate and the pixel electrode, a first capacitor electrode provided between the pixel electrode and the transistor, and be electrically connected to the pixel electrode and the transistor, a second capacitor electrode provided between the pixel electrode and the first capacitor electrode, be located so as to be opposite the first capacitor electrode via a capacitor insulating film, and be supplied with a predetermined electric potential, and a light-shielding film provided between the pixel electrode and the second capacitor electrode, be located so as to be at least partially overlapped by the transistor, and be electrically connected to the second capacitor electrode via a contact hole formed in an insulating film disposed between the second capacitor electrode and the light-shielding film.Type: ApplicationFiled: March 8, 2011Publication date: September 15, 2011Applicant: SEIKO EPSON CORPORATIONInventors: Minoru MORIWAKI, Masahiro YASUKAWA, Ken WAKITA
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Patent number: 7439114Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.Type: GrantFiled: August 18, 2005Date of Patent: October 21, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
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Patent number: 7061017Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.Type: GrantFiled: November 14, 2003Date of Patent: June 13, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
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Patent number: 7033872Abstract: A thin film transistor which can be used in an LCD display panel includes an insulator substrate, a gate electrode located on the insulator substrate, an insulator film provided on the insulator substrate and the gate electrode, and a polycrystalline silicon film located on the insulator film. A channel is defined in a first portion of the polycrystalline silicon film over the gate electrode, and a drain and a source are defined in second and third portions of the polycrystalline silicon film over the insulator substrate. Grain sizes of the drain and source are equal to or greater than a grain size of the channel.Type: GrantFiled: July 1, 2004Date of Patent: April 25, 2006Assignees: Sanyo Electric., Ltd., Sony CorporationInventors: Yushi Jinno, Ken Wakita, Masahiro Minegishi
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Publication number: 20050287825Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.Type: ApplicationFiled: August 18, 2005Publication date: December 29, 2005Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi kuwahara
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Publication number: 20050062047Abstract: A device has a first transistor and a second transistor wherein a channel length direction of the first transistor extends along a first direction and a channel length direction of the second transistor extends along a second direction intersecting the first direction, and the second transistor is formed on a same substrate as the first transistor. A first channel region and a second channel region are formed in semiconductor layers which are simultaneously formed and a mobility of the semiconductor film has an anisotropy in the first and second directions. With this structure, transistors having different mobilities can be obtained while using the semiconductor films formed on the same substrate and from a same material. For example, it is possible to form a transistor in which a high resistance is required using a semiconductor layer of the same characteristics as that in a transistor in which a high speed operation is desired, on the same substrate and with a minimum area.Type: ApplicationFiled: September 21, 2004Publication date: March 24, 2005Inventors: Ryuji Nishikawa, Kazuhiro Imao, Ken Wakita, Kiyoshi Yoneda
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Publication number: 20040241925Abstract: A thin film transistor which can be used in an LCD display panel includes an insulator substrate, a gate electrode located on the insulator substrate, an insulator film provided on the insulator substrate and the gate electrode, and a polycrystalline silicon film located on the insulator film. A channel is defined in a first portion of the polycrystalline silicon film over the gate electrode, and a drain and a source are defined in second and third portions of the polycrystalline silicon film over the insulator substrate. Grain sizes of the drain and source are equal to or greater than a grain size of the channel.Type: ApplicationFiled: July 1, 2004Publication date: December 2, 2004Applicants: Sanyo Electric Co., Ltd., Sony CorporationInventors: Yushi Jinno, Ken Wakita, Masahiro Minegishi
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Patent number: 6797651Abstract: A laser annealing apparatus is provided in which laser light is irradiated onto an amorphous semiconductor layer placed inside an annealing chamber through a chamber window, thereby poly-crystallizing the amorphous semiconductor film. Inside the annealing chamber a low degree vacuum (about 1.3×103 Pa to about 1.3 Pa) is maintained at a room temperature. An inert gas such as nitrogen, hydrogen, or argon is introduced into the atmosphere while maintaining the low degree vacuum. As a result, the surface smoothness of the polycrystalline semiconductor layer is comparable to that resulting from high degree vacuum annealing, while, unlike high degree vacuum annealing, there is less contamination of the chamber window and productivity is improved.Type: GrantFiled: February 22, 2002Date of Patent: September 28, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Takashi Hagino, Kazuhiro Imao, Ken Wakita, Toshio Monzen, Hidenori Ogata, Shiro Nakanishi, Yoshihiro Morimoto
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Publication number: 20040106246Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. Since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.Type: ApplicationFiled: November 14, 2003Publication date: June 3, 2004Applicant: Sanyo Electric Co., Ltd.Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
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Publication number: 20020142567Abstract: A laser annealing apparatus is provided in which laser light is irradiated onto an amorphous semiconductor layer placed inside an annealing chamber (100) through a chamber window (120), thereby poly-crystallizing the amorphous semiconductor film. Inside the annealing chamber 100 a low degree vacuum (about 1.3×103 Pa to about 1.3 Pa) is maintained at a room temperature. An inert gas such as nitrogen, hydrogen, or argon is introduced into the atmosphere while maintaining the low degree vacuum. As a result, the surface smoothness of the polycrystalline semiconductor layer is comparable to that resulting from high degree vacuum annealing, while, unlike high degree vacuum annealing, there is less contamination of the chamber window (120) and productivity is improved.Type: ApplicationFiled: February 22, 2002Publication date: October 3, 2002Inventors: Takashi Hagino, Kazuhiro Imao, Ken Wakita, Toshio Monzen, Hidenori Ogata, Shiro Nakanishi, Yoshihiro Morimoto
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Patent number: 6274414Abstract: For obtaining p-Si by irradiating a laser beam to an a-Si layer to polycrystallize, an energy level in a region to be irradiated by the laser beam is set such that a level at the rear area of the region along a scan direction of the laser beam is lower than that at the front area or the center area of the region. The energy level at the front area or the center area of the region is set such that it is substantially equal to or more than the upper limit energy level which maximizes a grain size of the p-Si obtained. since an energy profile is set as described above, when the laser beam is scanned on the a-Si layer, an irradiated energy of the laser on the region is gradually lowered from the upper limit as the laser beam passes through, which allows the semiconductor layer to be annealed within an optimal energy level during the latter half of the annealing process.Type: GrantFiled: August 14, 1997Date of Patent: August 14, 2001Assignee: Sanyo Electric Co., Ltd.Inventors: Hidenori Ogata, Ken Wakita, Kiyoshi Yoneda, Yoshihiro Morimoto, Tsutomu Yamada, Kazuhiro Imao, Takashi Kuwahara
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Publication number: 20010005020Abstract: A thin film transistor which can be used in an LCD display panel includes an insulator substrate, a gate electrode located on the insulator substrate, an insulator film provided on the insulator substrate and the gate electrode, and a polycrystalline silicon film located on the insulator film. A channel is defined in a first portion of the polycrystalline silicon film over the gate electrode, and a drain and a source are defined in second and third portions of the polycrystalline silicon film over the insulator substrate. Grain sizes of the drain and source are equal to or greater than a grain size of the channel.Type: ApplicationFiled: January 3, 2001Publication date: June 28, 2001Applicant: Sanyo Electric Co., Ltd.Inventors: Yushi Jinno, Ken Wakita, Masahiro Minegishi
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Patent number: 6207971Abstract: A thin film transistor which can be used in an LCD display panel includes an insulator substrate, a gate electrode located on the insulator substrate, an insulator film provided on the insulator substrate and the gate electrode, and a polycrystalline silicon film located on the insulator film. A channel is defined in a first portion of the polycrystalline silicon film over the gate electrode, and a drain and a source are defined in second and third portions of the polycrystalline silicon film over the insulator substrate. Grain sizes of the drain and source are equal to or greater than a grain size of the channel.Type: GrantFiled: December 24, 1997Date of Patent: March 27, 2001Assignees: Sanyo Electric Co., Ltd., Sony CorporationInventors: Yushi Jinno, Ken Wakita, Masahiro Minegishi
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Patent number: 6072194Abstract: Laser anneal processing of a semiconductor layer is repeated in a number of steps. Grain size is increased using high energy ELA for a first step, and grain sizes are uniformed using ELA with low energy for a later step. As a defective crystallization region occurs in an excessive energy region during the ELA for the first step, in the ELA for the second time, excessive energy is removed and the defective crystallization region is eliminated by reducing the energy to an optimal value, thereby improving the crystallinity of a p-Si layer.Type: GrantFiled: June 7, 1999Date of Patent: June 6, 2000Assignee: Sanyo Electric Co., Ltd.Inventors: Ken Wakita, Hidenori Ogata
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Patent number: 5960323Abstract: Laser anneal processing of a semiconductor layer is repeated in a number of steps. Grain size is increased using high energy ELA for a first step, and grain sizes are uniformed using ELA with low energy for a later step. As a defective crystallization region occurs in an excessive energy region during the ELA for the first step, in the ELA for the second time, excessive energy is removed and the defective crystallization region is eliminated by reducing the energy to an optimal value, thereby improving the crystallinity of a p-Si layer.Type: GrantFiled: June 17, 1997Date of Patent: September 28, 1999Assignee: Sanyo Electric Co., Ltd.Inventors: Ken Wakita, Hidenori Ogata