Abstract: A magnetic disk storage apparatus having a magnetic disk-type storage medium; a head for reading data recorded on the magnetic disk-type storage medium, a processor, a phase synchronizing circuit having a controllable response characteristic and for outputting a clock signal to handle the data read from the magnetic disk-type storage medium, and a memory for storing information to control the response characteristic of the phase synchronizing circuit previously set in accordance with an access position on the magnetic disk-type storage medium.

Abstract: A magnetic disk storage apparatus provides with a phase locked loop or a phase sync circuit including a phase comparator, a charge pump, a filter and a voltage-controlled oscillator. The phase sync circuit includes a register which is connected to an information processing system and adapted to store therein the response characteristics of the phase comparator, the charge pump, the filter and the voltage-controlled oscillator as instructed from the information processing system. In this way, in accordance with the information on the response characteristics from the information processing system, the phase sync circuit is controlled thereby to assure a stable operation even in the case of the data transfer speed varying between inner and outer track such as occurs in a magnetic disk.

Abstract: A differential circuit having a relatively simple structure capable of delivering a linear transfer characteristic and expanding an input dynamic range. An increase in magnitude of differential input voltage V.sub.in applied to each gate of differential-pair MOSFETs M1 and M2 in the differential circuit decreases control voltage V.sub.CONT in a control circuit. On the other hand, since a current fed to MOSFETs M3 and M4 in the differential circuit decreases simultaneously, a current supplied to the differential-pair MOSFETs M1 and M2 in the differential circuit increases. Thus, the present invention makes it possible to effectively expand the input dynamic range with respect to differential input voltage V.sub.in.

Abstract: Digital information including a sync data field and a user data field subsequent thereto is read from a storage media as a digital information signal in an analog signal format. The obtained signal is sampled according to a clock signal and is thereby transformed into a digital information signal in a digital format. In the sync data field, the clock signal is synchronized with the digital information signal by an analog PLL circuit. Thereafter, in the user data field, the clock signal is synchronized with the digital information signal by a digital PLL circuit.

Abstract: A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter.

Abstract: A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter.

Abstract: A magnetic disk storage apparatus provides with a phase locked loop or a phase sync circuit including a phase comparator, a charge pump, a filter and a voltage-controlled oscillator. The phase sync circuit includes a register which is connected to an information processing system and adapted to store therein the response characteristics of the phase comparator, the charge pump, the filter and the voltage-controlled oscillator as instructed from the information processing system. In this way, in accordance with the information on the response characteristics from the information processing system, the phase sync circuit is controlled thereby to assure a stable operation even in the case of the data transfer speed varying between inner and outer track such as occurs in a magnetic disk.

Abstract: An active filter control apparatus for controlling or tuning an active filter having a variable cut-off frequency. The active filter control apparatus includes a control circuit for controlling or tuning the cut-off frequency of the active filter and a characteristic correction generator for generating a correction signal to correct a group delay characteristic of the active filter in accordance with a set cut-off frequency. The characteristic correction includes a correction signal generator for generating the correction signal in accordance with a set correction amount. The cut-off frequency controller controls tunes the characteristic of the active filter in accordance with the correction signal. Preferably, the apparatus is formed of a one-chip LSI integrated on one chip. The control apparatus can be utilized to control the speed in a recording/reproducing apparatus such as a optical disk drive or a magnetic tape drive apparatus.

Abstract: In a signal processing unit for writing/reading data on/from a disk-shaped recording medium of a disk apparatus, all of a data separator, a code decoder circuit, a code encoder and a write compensation circuit are constructed on a one-chip integrated circuit. The data separator separates a synchronization clock from a code data reproduced from the disk. The code decoder circuit produces decoded data from the synchronization clock as the output from the data separator, and synchronized code data. The code encoder encodes data supplied from a host computer or a disk controller into code data. The write compensation circuit compensates for a peak shift with respect to write code data. This integrated circuit is fabricated by a Bipolar-CMOS process by which a bipolar transistor and a CMOS transistor are mixed with each other thereon.

Abstract: A data device for introducing the data read from a recording medium includes first creation device for receiving a read code signal corresponding to the data stored on a data recording medium to create first two phase signals which repeat inversion with a substantially equal period to each other on the basis of a change in the waveform of the read code; second creation device for receiving the first two phase signals to create second two phase signals with their one phase occupying most of their period having an overlapping portion with each other, the period being twice as long as that of the first two phase signals; and third creation device for receiving the read code signal and said second two phase signals to create a second code signal corresponding to the read code signal which shifts during the one phase period of said second two phase signals.

Abstract: A magnetic disk system which records and reproduces data on a magnetic disk at different data transfer rates depending on a track position on the disk includes a transversal waveform equalizing circuit which implements an optimal waveform shaping for a readout waveform. The waveform equalizing circuit consists of a register, a frequency synthesizer, a PLL, and a transversal circuit. The transversal circuit consists of variable delay circuits, variable gain amplifiers, and an adder. The frequency synthesizer produces a write clock signal having a frequency which corresponds to a value stored in the register which depends on the data transfer rate, and the PLL responds to the write clock signal to produce a control signal by which the delay time of the transversal circuit is controlled.

Abstract: A magnetic disk storage apparatus provides with a phase locked loop or a phase sync circuit including a phase comparator, a charge pump, a filter and a voltage-controlled oscillator. The phase sync circuit includes a register which is connected to an information processing system and adapted to store therein the response characteristics of the phase comparator, the charge pump, the filter and the voltage-controlled oscillator as instructed from the information processing system. In this way, in accordance with the information on the response characteristics from the information processing system, the phase sync circuit is controlled thereby to assure a stable operation even in the case of the data transfer speed varying between inner and outer track such as occurs in a magnetic disk.

Abstract: In a signal processing unit for writing/reading data on/from a disk-shaped recording medium of a disk apparatus, all of a data separator, a code decoder circuit, a code encoder and a write compensation circuit are constructed on a one-chip integrated circuit. The data separator separates a synchronization clock from a code data reproduced from the disk. The code decoder circuit produces decoded data from the synchronization clock as the output from the data separator, and synchronized code data. The code encoder encodes data supplied from a host computer or a disk controller into code data. The write compensation circuit compensates for a peak shift with respect to write code data. This integrated circuit is fabricated by a Bipolar-CMOS process by which a bipolar transistor and a CMOS transistor are mixed with each other thereon.

Abstract: Pulse detector and a data separator are integrated on a single chip semiconductor integrated circuit. In the pulse detector, an input stage of a gain variable amplifier, which amplifies an input signal applied thereto so as to have a constant peak, includes a bipolar transistor, and a pulse generator for generating a pulse shape signal according to a differential value of an output from the gain variable amplifier includes a Bi-CMOS gate or a CMOS gate. In the data separator, a voltage controlled oscillator for generating a clock signal includes a bipolar transistor. A frequency phase comparator for comparing the pulse shape signal in phases with the clock signal generated by the voltage controlled oscillator to obtain a phase difference, includes a Bi-CMOS gate and a CMOS gate.

Abstract: In a signal processing unit for writing/reading data on/from a disk-shaped recording medium of a disk apparatus, all of a data separator, a code decoder circuit, a code encoder and a write compensation circuit are constructed on a one-chip integrated circuit. The data separator separates a synchronization clock from a code data reproduced from the disk. The code decoder circuit produces decoded data from the synchronization clock as the output from the data separator, and synchronized code data. The code encoder encodes data supplied from a host computer or a disk controller into code data. The write compensation circuit compensates for a peak shift with respect to write code data. This integrated circuit is fabricated by a Bipolar-CMOS process by which a bipolar transistor and a CMOS transistor are mixed with each other thereon.

Abstract: When data are memorized in a 2-7 RLL code on a disc shaped memorizing medium using a sector format, as an address mark in each sector a 2-7 illegal pattern is used; a 1-byte data "8B" in an NRZ signal is converted into a 2-7 RLL code, and further it is modified into the 2-7 illegal pattern.A disc controller in a disc memory inserts the 1-byte data "8B" into a specified position in an NRZ signal and transmits it to an encoder/decoder. In the encoder, the 1-byte data "8B" in an NRZ signal is detected, and a 2-7 illegal pattern is formed by reversing a specified bit of a 2-7 RLL code formed by converting the 1-byte data "8B", and the illegal pattern is sent to the read/write amplifier.