Patents by Inventor Kenichi Hidaka

Kenichi Hidaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210024929
    Abstract: Developed and provided is: a nucleic acid agent that is efficiently delivered to the central nervous system, to which drug delivery is inhibited by the blood brain barrier mechanism, and that provides an antisense effect to a target transcription product at the delivery site; and a composition containing such a nucleic acid agent. Provided is a double-stranded nucleic acid complex consisting of a first nucleic acid strand and a second nucleic acid strand that are annealed to each other; wherein the first nucleic acid strand hybridizes with part of a target transcription product and has an antisense effect on the target transcription product; and wherein the second nucleic acid strand includes a base sequence complementary to the first nucleic acid strand and is conjugated to a phosphatidylethanolamine or an analog thereof.
    Type: Application
    Filed: March 13, 2019
    Publication date: January 28, 2021
    Applicants: National University Corporation Tokyo Medical and Dental University, Takeda Pharmaceutical Company Limited
    Inventors: Takanori Yokota, Tetsuya Nagata, Hideki Furukawa, Yasuo Nakagawa, Takatoshi Yogo, Ryosuke Tokunoh, Shigekazu Sasaki, Kosuke Hidaka, Tomohiro Seki, Kenichi Miyata, Akio Uchida
  • Publication number: 20200290017
    Abstract: A porous ceramic structure with low pressure loss and high catalytic performance is provided. The porous ceramic structure includes a porous structure body (i.e., honeycomb structure) composed primarily of cordierite, and manganese (Mn) and tungsten (W) that are fixedly attached to the honeycomb structure. Thus, pressure loss in the porous ceramic structure can be reduced, and an NO combustion temperature in the porous ceramic structure can be lowered. In other words, the aforementioned structure of the porous ceramic structure allows the porous ceramic structure to have low pressure loss and high catalytic performance.
    Type: Application
    Filed: March 3, 2020
    Publication date: September 17, 2020
    Applicant: NGK INSULATORS, LTD.
    Inventors: YUNIE IZUMI, Kenichi Hidaka
  • Patent number: 10632648
    Abstract: A ceramic formed body extrusion method for forming a ceramic formed body having a wall-shaped or plate-shaped formed portion by using an extrusion die provided with a slit for extrusion of a ceramic formed body from a raw material for forming, the slit including a slit former stage unit located on an upstream side in an extrusion direction in the extrusion and a slit latter stage unit located on a downstream side in the extrusion direction, the slit latter stage unit having a width of three to 27 times a width of the slit former stage unit, and by extruding a raw material containing a first particle having an aspect ratio of two or more and less than 300 such that the raw material passes though the slit former stage unit of the extrusion die and then passes through the slit latter stage unit.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: April 28, 2020
    Assignee: NGK Insulators, Ltd.
    Inventors: Takafumi Kimata, Kenichi Hidaka, Yoshio Kikuchi, Masaki Ishikawa, Kisuke Yamamoto, Kenji Morimoto
  • Patent number: 10596722
    Abstract: A ceramic formed body extrusion method for forming a ceramic formed body having a wall-shaped or plate-shaped formed portion by using an extrusion die provided with a slit for extrusion of a ceramic formed body from a raw material for forming, the slit including a slit former stage unit located on an upstream side in an extrusion direction in the extrusion and a slit latter stage unit located on a downstream side in the extrusion direction, the slit latter stage unit having a width of three to 27 times a width of the slit former stage unit, and by extruding a raw material containing a first particle having an aspect ratio of two or more and less than 300 such that the raw material passes though the slit former stage unit of the extrusion die and then passes through the slit latter stage unit.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: March 24, 2020
    Assignee: NGK Insulators, Ltd.
    Inventors: Takafumi Kimata, Kenichi Hidaka, Yoshio Kikuchi, Masaki Ishikawa, Kisuke Yamamoto, Kenji Morimoto
  • Publication number: 20190351577
    Abstract: A ceramic formed body extrusion method for forming a ceramic formed body having a wall-shaped or plate-shaped formed portion by using an extrusion die provided with a slit for extrusion of a ceramic formed body from a raw material for forming, the slit including a slit former stage unit located on an upstream side in an extrusion direction in the extrusion and a slit latter stage unit located on a downstream side in the extrusion direction, the slit latter stage unit having a width of three to 27 times a width of the slit former stage unit, and by extruding a raw material containing a first particle having an aspect ratio of two or more and less than 300 such that the raw material passes though the slit former stage unit of the extrusion die and then passes through the slit latter stage unit.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 21, 2019
    Applicant: NGK Insulators, Ltd.
    Inventors: Takafumi KIMATA, Kenichi HIDAKA, Yoshio KIKUCHI, Masaki ISHIKAWA, Kisuke YAMAMOTO, Kenji MORIMOTO
  • Publication number: 20190351578
    Abstract: A ceramic formed body extrusion method for forming a ceramic formed body having a wall-shaped or plate-shaped formed portion by using an extrusion die provided with a slit for extrusion of a ceramic formed body from a raw material for forming, the slit including a slit former stage unit located on an upstream side in an extrusion direction in the extrusion and a slit latter stage unit located on a downstream side in the extrusion direction, the slit latter stage unit having a width of three to 27 times a width of the slit former stage unit, and by extruding a raw material containing a first particle having an aspect ratio of two or more and less than 300 such that the raw material passes though the slit former stage unit of the extrusion die and then passes through the slit latter stage unit.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 21, 2019
    Applicant: NGK Insulators, Ltd.
    Inventors: Takafumi KIMATA, Kenichi HIDAKA, Yoshio KIKUCHI, Masaki ISHIKAWA, Kisuke YAMAMOTO, Kenji MORIMOTO
  • Patent number: 10421213
    Abstract: A ceramic formed body extrusion method for forming a ceramic formed body having a wall-shaped or plate-shaped formed portion by using an extrusion die provided with a slit for extrusion of a ceramic formed body from a raw material for forming, the slit including a slit former stage unit located on an upstream side in an extrusion direction in the extrusion and a slit latter stage unit located on a downstream side in the extrusion direction, the slit latter stage unit having a width of three to 27 times a width of the slit former stage unit, and by extruding a raw material containing a first particle having an aspect ratio of two or more and less than 300 such that the raw material passes though the slit former stage unit of the extrusion die and then passes through the slit latter stage unit.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: September 24, 2019
    Assignee: NGK Insulators, Ltd.
    Inventors: Takafumi Kimata, Kenichi Hidaka, Yoshio Kikuchi, Masaki Ishikawa, Kisuke Yamamoto, Kenji Morimoto
  • Patent number: 10413835
    Abstract: The present invention provides a game system having a communication function that takes into account player operability. A game device on which a mah-jongg game is executed holds registered comment information in which a plurality of registered comments are associated with a predetermined particular state in the mah-jongg game, and when a current game state transitions to the particular state, displays the plurality of registered comments associated with the particular state on a game screen. Delivery information that includes a registered comment selected by a player as a transmission comment is then sent to a server. The server holds a plurality of delivery destination addresses to which the delivery information of the player is to be sent via an open network, and when the delivery information is received from the game device, delivers the delivery information to each delivery destination address pertaining to the player corresponding to the delivery information.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: September 17, 2019
    Assignee: KONAMI DIGITAL ENTERTAINMENT CO., LTD.
    Inventors: Shota Hidaka, Masakazu Shibamiya, Kenichi Yamamoto
  • Publication number: 20170282402
    Abstract: A ceramic formed body extrusion method for forming a ceramic formed body having a wall-shaped or plate-shaped formed portion by using an extrusion die provided with a slit for extrusion of a ceramic formed body from a raw material for forming, the slit including a slit former stage unit located on an upstream side in an extrusion direction in the extrusion and a slit latter stage unit located on a downstream side in the extrusion direction, the slit latter stage unit having a width of three to 27 times a width of the slit former stage unit, and by extruding a raw material containing a first particle having an aspect ratio of two or more and less than 300 such that the raw material passes though the slit former stage unit of the extrusion die and then passes through the slit latter stage unit.
    Type: Application
    Filed: March 28, 2017
    Publication date: October 5, 2017
    Applicant: NGK INSULATORS, LTD.
    Inventors: Takafumi KIMATA, Kenichi HIDAKA, Yoshio KIKUCHI, Masaki ISHIKAWA, Kisuke YAMAMOTO, Kenji MORIMOTO
  • Patent number: 9349739
    Abstract: The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor via a line, and a capacitor coupled to the first node. By applying high voltage which does not break but deteriorates a gate oxide film and increases gate leak current to a memory transistor, data is written. Data can be read by the presence/absence of leak of charges accumulated in the capacitor. Since the position of deterioration in the gate oxide film cannot be discriminated by a physical analysis, confidentiality is high.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: May 24, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Hidaka, Yoshitaka Kubota
  • Patent number: 9339799
    Abstract: To provide a honeycomb structure capable of using as a catalyst carrier, which functions as a heater, and where a bonding layer is hard to break and an electrical resistance value is hard to rise; including a honeycomb segment bonded body where honeycomb segments are bonded by bonding layer, and a pair of electrode members disposed on a side surface of the bonded body, the electrode members is formed into a band shape, and in a cross section perpendicular to the cell extending direction, one electrode member is disposed on an opposite side across the center of the bonded body to another electrode member, and in at least a part of the bonding layer, inorganic fibers made of ?-SiC and a metal silicide are included in a porous body where silicon carbide are bound with silicon in a state where pores are held among the particles.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: May 17, 2016
    Assignee: NGK Insulators, Ltd.
    Inventors: Yoshio Kikuchi, Hiroharu Kobayashi, Kenichi Hidaka, Miyuki Kojima, Yoshimasa Kobayashi
  • Patent number: 9289754
    Abstract: To provide a honeycomb structure capable of using as a catalyst carrier, which suitably functions as a heater by applying a voltage, and where a bonding layer is hard to break; and including a honeycomb segment bonded body where honeycomb segments are bonded by bonding layer, and a pair of electrode members disposed on side surface of the bonded body, wherein the electrode members is formed into a band shape, in a cross section perpendicular to the cell extending direction, the one electrode member is disposed on an opposite side across the center of the bonded body with respect to another electrode member, and in at least a part of the bonding layer, inorganic fibers made of an oxide are included in a porous body where particles of silicon carbide are bound with silicon in a state where pores are held among the particles.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: March 22, 2016
    Assignee: NGK Insulators, Ltd.
    Inventors: Yoshio Kikuchi, Kenichi Hidaka
  • Publication number: 20150311216
    Abstract: The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor via a line, and a capacitor coupled to the first node. By applying high voltage which does not break but deteriorates a gate oxide film and increases gate leak current to a memory transistor, data is written. Data can be read by the presence/absence of leak of charges accumulated in the capacitor. Since the position of deterioration in the gate oxide film cannot be discriminated by a physical analysis, confidentiality is high.
    Type: Application
    Filed: July 6, 2015
    Publication date: October 29, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Kenichi HIDAKA, Yoshitaka KUBOTA
  • Patent number: 9105338
    Abstract: The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor via a line, and a capacitor coupled to the first node. By applying high voltage which does not break but deteriorates a gate oxide film and increases gate leak current to a memory transistor, data is written. Data can be read by the presence/absence of leak of charges accumulated in the capacitor. Since the position of deterioration in the gate oxide film cannot be discriminated by a physical analysis, confidentiality is high.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: August 11, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Hidaka, Yoshitaka Kubota
  • Patent number: 8982648
    Abstract: An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: March 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takuji Onuma, Kenichi Hidaka, Hiromichi Takaoka, Yoshitaka Kubota, Hiroshi Tsuda
  • Patent number: 8942023
    Abstract: A semiconductor device using resistive random access memory (ReRAM) elements and having improved tamper resistance is provided. The semiconductor device is provided with a unit cell which stores one bit of cell data and a control circuit. The unit cell includes n ReRAM elements (n being an integer of 2 or larger). At least one of the ReRAM elements is an effective element where the cell data is recorded. In reading the cell data, the control circuit at least selects the effective element and reads data recorded thereon as the cell data.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: January 27, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Tsuda, Yoshitaka Kubota, Kenichi Hidaka, Hiromichi Takaoka
  • Publication number: 20140296054
    Abstract: To provide a honeycomb structure capable of using as a catalyst carrier, which suitably functions as a heater by applying a voltage, and where a bonding layer is hard to break; and including a honeycomb segment bonded body where honeycomb segments are bonded by bonding layer, and a pair of electrode members disposed on side surface of the bonded body, wherein the electrode members is formed into a band shape, in a cross section perpendicular to the cell extending direction, the one electrode member is disposed on an opposite side across the center of the bonded body with respect to another electrode member, and in at least a part of the bonding layer, inorganic fibers made of an oxide are included in a porous body where particles of silicon carbide are bound with silicon in a state where pores are held among the particles.
    Type: Application
    Filed: March 21, 2014
    Publication date: October 2, 2014
    Applicant: NGK Insulators, Ltd.
    Inventors: Yoshio KIKUCHI, Kenichi HIDAKA
  • Publication number: 20140296055
    Abstract: To provide a honeycomb structure capable of using as a catalyst carrier, which functions as a heater, and where a bonding layer is hard to break and an electrical resistance value is hard to rise; including a honeycomb segment bonded body where honeycomb segments are bonded by bonding layer, and a pair of electrode members disposed on a side surface of the bonded body, the electrode members is formed into a band shape, and in a cross section perpendicular to the cell extending direction, one electrode member is disposed on an opposite side across the center of the bonded body to another electrode member, and in at least a part of the bonding layer, inorganic fibers made of ?-SiC and a metal silicide are included in a porous body where silicon carbide are bound with silicon in a state where pores are held among the particles.
    Type: Application
    Filed: March 21, 2014
    Publication date: October 2, 2014
    Applicant: NGK Insulators, Ltd.
    Inventors: Yoshio KIKUCHI, Hiroharu KOBAYASHI, Kenichi HIDAKA, Miyuki KOJIMA, Yoshimasa KOBAYASHI
  • Patent number: 8675385
    Abstract: A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: March 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiromichi Takaoka, Kenichi Hidaka, Hiroshi Tsuda, Kiyokazu Ishige, Yoshitaka Kubota, Takuji Onuma
  • Patent number: 8592942
    Abstract: A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: November 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Noriaki Kodama, Kenichi Hidaka, Hiroyuki Kobatake, Takuji Onuma