Patents by Inventor Kenichi Hisada
Kenichi Hisada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369414Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region. a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Inventors: Atsushi SAKAI, Katsumi EIKYU, Yasuhiro OKAMOTO, Kenichi HISADA, Nobuo MACHIDA
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Publication number: 20230207689Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.Type: ApplicationFiled: February 27, 2023Publication date: June 29, 2023Inventors: Kenichi HISADA, Koichi ARAI, Hironobu MIYAMOTO
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Patent number: 11631764Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.Type: GrantFiled: October 1, 2020Date of Patent: April 18, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kenichi Hisada, Koichi Arai, Hironobu Miyamoto
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Publication number: 20230077367Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.Type: ApplicationFiled: November 21, 2022Publication date: March 16, 2023Inventors: Yasuhiro OKAMOTO, Nobuo MACHIDA, Koichi ARAI, Kenichi HISADA, Yasunori YAMASHITA, Satoshi EGUCHI, Hironobu MIYAMOTO, Atsushi SAKAI, Katsumi EIKYU
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Patent number: 11276784Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.Type: GrantFiled: December 14, 2020Date of Patent: March 15, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yasuhiro Okamoto, Nobuo Machida, Kenichi Hisada
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Publication number: 20210217888Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.Type: ApplicationFiled: March 29, 2021Publication date: July 15, 2021Inventors: Atsushi SAKAI, Katsumi EIKYU, Satoshi EGUCHI, Nobuo MACHIDA, Koichi ARAI, Yasuhiro OKAMOTO, Kenichi HISADA, Yasunori YAMASHITA
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Publication number: 20210135018Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.Type: ApplicationFiled: December 14, 2020Publication date: May 6, 2021Inventors: Yasuhiro OKAMOTO, Nobuo MACHIDA, Kenichi HISADA
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Publication number: 20210074816Abstract: Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region. a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.Type: ApplicationFiled: August 18, 2020Publication date: March 11, 2021Inventors: Atsushi SAKAI, Katsumi EIKYU, Yasuhiro OKAMOTO, Kenichi HISADA, Nobuo MACHIDA
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Publication number: 20210028306Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.Type: ApplicationFiled: October 1, 2020Publication date: January 28, 2021Inventors: Kenichi HISADA, Koichi ARAI, Hironobu MIYAMOTO
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Patent number: 10896980Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.Type: GrantFiled: October 10, 2019Date of Patent: January 19, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yasuhiro Okamoto, Nobuo Machida, Kenichi Hisada
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Patent number: 10833188Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.Type: GrantFiled: February 22, 2019Date of Patent: November 10, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kenichi Hisada, Koichi Arai, Hironobu Miyamoto
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Publication number: 20200161445Abstract: An n-type epitaxial layer is formed on an n-type semiconductor substrate made of silicon carbide. p-type body regions are formed in the epitaxial layer, and n-type source region is formed in the body region. On the body region between the source region and the epitaxial layer, a gate electrode is formed via a gate dielectric film, and an interlayer insulating film having an opening is formed so as to cover the gate electrode. A source electrode electrically connected to the source region and the body regions is formed in the opening. A recombination layer is formed between the body region and a basal plane dislocation is a layer having point defect density higher than that of the epitaxial layer located directly under the recombination layer or having a metal added to the epitaxial layer.Type: ApplicationFiled: October 9, 2019Publication date: May 21, 2020Inventors: Hironobu MIYAMOTO, Yasuhiro OKAMOTO, Kenichi HISADA, Koichi ARAI, Nobuo MACHIDA
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Publication number: 20200161480Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.Type: ApplicationFiled: October 10, 2019Publication date: May 21, 2020Inventors: Yasuhiro OKAMOTO, Nobuo MACHIDA, Kenichi HISADA
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Publication number: 20200020781Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate made of silicon carbide; a second conductivity type body region in a device region of the semiconductor substrate; a first conductivity type source region formed in the body region; and a gate electrode formed on the body region through gate insulating films. The semiconductor device further includes, in a termination region of the semiconductor substrate, second conductivity type RESURF layers, and an edge termination region formed in the RESURF layers. Then, the RESURF layers and a front surface of the semiconductor substrate adjacent to the RESURF layers are covered by an oxidation-resistant insulating film.Type: ApplicationFiled: September 23, 2019Publication date: January 16, 2020Inventors: Kenichi HISADA, Koichi ARAI
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Patent number: 10468496Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate made of silicon carbide; a second conductivity type body region in a device region of the semiconductor substrate; a first conductivity type source region formed in the body region; and a gate electrode formed on the body region through gate insulating films. The semiconductor device further includes, in a termination region of the semiconductor substrate, second conductivity type RESURF layers, and an edge termination region formed in the RESURF layers. Then, the RESURF layers and a front surface of the semiconductor substrate adjacent to the RESURF layers are covered by an oxidation-resistant insulating film.Type: GrantFiled: October 23, 2017Date of Patent: November 5, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kenichi Hisada, Koichi Arai
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Publication number: 20190288105Abstract: First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.Type: ApplicationFiled: February 22, 2019Publication date: September 19, 2019Inventors: Kenichi HISADA, Koichi ARAI, Hironobu MIYAMOTO
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Publication number: 20190237577Abstract: A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.Type: ApplicationFiled: December 18, 2018Publication date: August 1, 2019Inventors: Yasuhiro OKAMOTO, Nobuo MACHIDA, Koichi ARAI, Kenichi HISADA, Yasunori YAMASHITA, Satoshi EGUCHI, Hironobu MIYAMOTO, Atsushi SAKAI, Katsumi EIKYU
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Publication number: 20190198663Abstract: To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.Type: ApplicationFiled: November 15, 2018Publication date: June 27, 2019Inventors: Atsushi SAKAI, Katsumi EIKYU, Satoshi EGUCHI, Nobuo MACHIDA, Koichi ARAI, Yasuhiro OKAMOTO, Kenichi HISADA, Yasunori YAMASHITA
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Patent number: 10256339Abstract: In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film formed so as to cover a corner of the trench is made thicker than the film thickness of apart of the gate insulating film part formed on/over a side face of the trench.Type: GrantFiled: September 20, 2018Date of Patent: April 9, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yasunori Yamashita, Koichi Arai, Kenichi Hisada
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Publication number: 20190096998Abstract: A method for manufacturing a semiconductor device includes the steps of forming a metal film (Ni film) over the bottom surface of a contact hole that exposes a portion including SiC at the bottom surface, and performing a heat treatment to form a silicide film at the bottom surface of the contact hole by a silicidation reaction of the metal film MT and the portion including SiC. Also, the heat treatment step is a step of irradiating a laser beam on the surface of a SiC substrate. As the heat treatment, annealing is performed using the laser beam that goes through SiC and is absorbed by metal (Ni and the like).Type: ApplicationFiled: July 13, 2018Publication date: March 28, 2019Inventors: Yuji FUJII, Kenichi Hisada, Yasunori Yanashita