Patents by Inventor Kenichi Kaneda
Kenichi Kaneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250040518Abstract: There is provided a health condition determination apparatus including: a behavior data acquisition part that acquires behavior data indicating a behavior of an animal acquired by executing at least one of monitoring and sensing on the animal; a behavior data accumulation part that accumulates the behavior data; and a health condition estimation part that estimates a health condition of the animal by using the behavior data.Type: ApplicationFiled: December 16, 2022Publication date: February 6, 2025Applicant: NEC Communication Systems, Ltd.Inventors: Masakazu KANEDA, Kenichi ABE, Momo SUTO, Chikashi ITO, Tetsuya ITO, Akira MATSUMOTO, Norihiko KAMATA, Satoki UENO
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Patent number: 12216843Abstract: An electronic pen includes a circuit board disposed such that an axial direction of a casing is aligned with a longitudinal direction of the circuit board, an electronic circuit on the circuit board, and a battery having a columnar shape disposed on a side of the circuit board opposite to a pen tip side of the circuit board inside a hollow portion of the casing such that positive and negative electrode conductors protruding from an end surface of the battery extend toward the circuit board. The battery is disposed such that a separation space is formed between the end surface and an end portion of the circuit board and such that tip portions of the positive and negative electrode conductors are in contact with the circuit board. The circuit board and the tip portions of the positive and negative electrode conductors are electrically connected to each other by soldered portions.Type: GrantFiled: November 14, 2023Date of Patent: February 4, 2025Assignee: Wacom Co., Ltd.Inventors: Kohei Tanaka, Takayuki Arai, Kenichi Ninomiya, Takenori Kaneda
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Patent number: 12203825Abstract: A pressure detection element of a capacitive system includes a dielectric having two opposing surfaces including a first surface and a second surface, a conductor layer provided on the first surface of the dielectric, a conductive elastic member provided on the second surface of the dielectric, a spacer that positions the conductive elastic member at a predetermined distance from the second surface of the dielectric, and a pressing member configured to push the conductive elastic member toward the dielectric. An end surface of the pressing member that presses the conductive elastic member has a predetermined curvature, with an apex at a center of the end surface. A protrusion is provided at the apex at the center of the end surface of the pressing member.Type: GrantFiled: January 12, 2024Date of Patent: January 21, 2025Assignee: Wacom Co., Ltd.Inventors: Takenori Kaneda, Kenichi Ninomiya, Kohei Tanaka
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Patent number: 12204702Abstract: An electronic pen includes a casing, an opening portion formed on one side of the casing, a core body that projects outside of the casing through the opening portion, a pen module part, and a core body insertion member disposed in the casing and having a hollow space that houses the core body. The hollow space includes a hollow portion between an inner circumferential surface of the core body insertion member and an outer circumferential surface of the core body when the core body insertion member houses the core body, the hollow portion communicating, via the opening portion, with a first space external to the electronic pen. The hollow portion is separated from a second space in which the pen module part is disposed within the casing.Type: GrantFiled: October 13, 2023Date of Patent: January 21, 2025Assignee: Wacom Co., Ltd.Inventors: Kenichi Ninomiya, Takayuki Arai, Kohei Tanaka, Takenori Kaneda
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Publication number: 20250021917Abstract: An evaluation apparatus includes: an evaluation method acquisition part configured to acquire evaluation method data from an evaluation method provision apparatus; an evaluation criteria creation part configured to create evaluation criteria information for evaluating collected information that integrates data collected from a field management system that manages field information based on the evaluation method data; an evaluation processing part configured to evaluate the collected information based on the evaluation criteria information and create an evaluation result.Type: ApplicationFiled: December 16, 2022Publication date: January 16, 2025Applicant: NEC Communication Systems, Ltd.Inventors: Akira MATSUMOTO, Momo Suto, Kenichi Abe, Chikashi Ito, Tetsuya Ito, Norihiko Kamata, Masakazu Kaneda, Satoki Ueno
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Patent number: 8754337Abstract: An object of the invention is to provide a method for fabricating a printed wiring board that can suppress warping of the printed wiring board and can improve the yield of semiconductor chip mounting and enhance the reliability of a semiconductor package. The printed wiring board fabrication method according to the invention is a method for fabricating a printed wiring board having a through-hole in a core layer, wherein the printed wiring board fabrication method includes the step of applying a laser from one side of the core layer to a position where the through-hole is to be formed in the core layer and the step of applying a laser to the same position from the opposite side of the core layer.Type: GrantFiled: March 26, 2010Date of Patent: June 17, 2014Assignee: Sumitomo Bakelite Co., Ltd.Inventor: Kenichi Kaneda
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Patent number: 8455765Abstract: A laminated body of the present invention includes a resin layer in which a core portion composed of a fiber base member having a thickness of 25 ?m or less is embedded, the resin layer having two surfaces, and the resin layer through which at least one via-hole is adapted to be formed, and a metal layer bonded to at least one of the two surfaces of the resin layer, and the metal layer having at least one opening portion provided so as to correspond to the via-hole to be formed. Further, a method of manufacturing a substrate of the present invention includes preparing the above laminated body, forming the via-hole so as to pass through the resin layer by irradiating a laser beam onto the resin layer, and removing the metal layer from the resin layer after the via-hole is formed. Further, a substrate of the present invention is manufactured by using the above method. Furthermore, a semiconductor device of the present invention includes the above substrate, and a semiconductor element mounted on the substrate.Type: GrantFiled: January 23, 2008Date of Patent: June 4, 2013Assignee: Sumitomo Bakelite Company, Ltd.Inventors: Junpei Morimoto, Kenichi Kaneda
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Patent number: 8425790Abstract: An ink composition for ink jet printing is provided which gives a cured object excellent in adhesion to metallic plates, resistance to etchants, and alkali removability and can be stably ejected with an ink jet apparatus. The ink jet composition for etching resists has a viscosity at 25° C. of 3-50 mPa s and includes monomers comprising: either a polymerizable phosphoric ester compound represented by general formula (I); a polyfunctional monomer having two or more ethylenic double-bond groups per molecule and having no phosphoric ester group, the content of the ethylenic double-bond groups being 4×10?3 to 8×10?3 mol/g; and a monofunctional monomer having one ethylenic double-bond group per molecule and having neither phosphoric ester group nor carboxy group. In the formula, X represents C1-3 alkylene, Y represents C2-3 alkylene, and R represents hydrogen or methyl.Type: GrantFiled: January 27, 2009Date of Patent: April 23, 2013Assignees: Nisshin Steel Co., Ltd., Tokyo Printing Ink Mfg. Co., Ltd.Inventors: Masaki Sato, Seiju Suzuki, Shuichi Sugita, Kenichi Kaneda, Shigenori Kobayashi
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Publication number: 20120037413Abstract: An object of the invention is to provide a method for fabricating a printed wiring board that can suppress warping of the printed wiring board and can improve the yield of semiconductor chip mounting and enhance the reliability of a semiconductor package. The printed wiring board fabrication method according to the invention is a method for fabricating a printed wiring board having a through-hole in a core layer, wherein the printed wiring board fabrication method includes the step of applying a laser from one side of the core layer to a position where the through-hole is to be formed in the core layer and the step of applying a laser to the same position from the opposite side of the core layer.Type: ApplicationFiled: March 26, 2010Publication date: February 16, 2012Inventor: Kenichi Kaneda
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Publication number: 20110308848Abstract: Disclosed are a composite body, a method for producing the composite body and a semiconductor device, the composite body comprising a resin layer and a fine wiring and/or via hole being formed in the resin layer, having high adhesion and high reliability, and being capable of high frequencies. Also disclosed are a resin composition and a resin sheet, both of which can provide such a composite body. The composite body comprises a resin layer and an electroconductive layer, wherein a groove having a maximum width of 1 ?m or more and 10 ?m or less is on a surface of the resin layer; the electroconductive layer is inside the groove; and a surface of the resin layer being in contact with the electroconductive layer has an arithmetic average roughness (Ra) of 0.05 ?m or more and 0.Type: ApplicationFiled: February 8, 2010Publication date: December 22, 2011Applicant: SUMITOMO BAKELITE COMPANY, LTD.Inventors: Yuka Ito, Kenichi Kaneda, Yasuaki Mitsui, Iji Onozuka, Noriyuki Ohigashi, Hideki Hara
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Publication number: 20110180208Abstract: A method for laminating a prepreg contributing to decrease in layer thickness and having high productivity, a method for producing a printed wiring board by the method for laminating the prepreg, and a prepreg roll used for the method for laminating the prepreg are provided.Type: ApplicationFiled: January 20, 2011Publication date: July 28, 2011Inventors: Kenya TACHIBANA, Kuniharu UMENO, Kenichi KANEDA
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Publication number: 20110024392Abstract: An ink composition for ink jet printing is provided which gives a cured object excellent in adhesion to metallic plates, resistance to etchants, and alkali removability and can be stably ejected with an ink jet apparatus. The ink jet composition for etching resists has a viscosity at 25° C. of 3-50 mPa s and includes monomers comprising: either a polymerizable phosphoric ester compound represented by general formula (I); a polyfunctional monomer having two or more ethylenic double-bond groups per molecule and having no phosphoric ester group, the content of the ethylenic double-bond groups being 4×10?3 to 8×10?3 mol/g; and a monofunctional monomer having one ethylenic double-bond group per molecule and having neither phosphoric ester group nor carboxy group. In the formula, X represents C1-3 alkylene, Y represents C2-3 alkylene, and R represents hydrogen or methyl.Type: ApplicationFiled: January 27, 2009Publication date: February 3, 2011Inventors: Masaki Sato, Seiju Suzuki, Shuichi Sugita, Kenichi Kaneda, Shigenori Kobayashi
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Publication number: 20100044081Abstract: A laminated body of the present invention includes a resin layer in which a core portion composed of a fiber base member having a thickness of 25 ?m or less is embedded, the resin layer having two surfaces, and the resin layer through which at least one via-hole is adapted to be formed, and a metal layer bonded to at least one of the two surfaces of the resin layer, and the metal layer having at least one opening portion provided so as to correspond to the via-hole to be formed. Further, a method of manufacturing a substrate of the present invention includes preparing the above laminated body, forming the via-hole so as to pass through the resin layer by irradiating a laser beam onto the resin layer, and removing the metal layer from the resin layer after the via-hole is formed. Further, a substrate of the present invention is manufactured by using the above method. Furthermore, a semiconductor device of the present invention includes the above substrate, and a semiconductor element mounted on the substrate.Type: ApplicationFiled: January 23, 2008Publication date: February 25, 2010Applicant: SUMITOMO BAKELITE COMPANY LIMITEDInventors: Junpei Morimoto, Kenichi Kaneda
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Patent number: 5302852Abstract: A semiconductor device includes a semiconductor element, a base, a cap, leads, and low-melting glass. The semiconductor element is mounted on the base, and the base consists of high-purity alumina and has a thickness of 0.5 mm or less. The cap is arranged on the base to cover the semiconductor element, consists of translucent alumina, and has a thickness of 0.4 mm or less. The leads extend out of the semiconductor device to be interposed between the base and the cap, and are electrically connected to the semiconductor element. The low-melting glass integrally and hermetically seals the base, the leads, and the cap.Type: GrantFiled: February 23, 1993Date of Patent: April 12, 1994Assignee: NEC CorporationInventors: Kenichi Kaneda, Akio Tanda
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Patent number: 5284899Abstract: A resin paste for tight sealing, comprising(A) at least one filler selected from the group consisting of Ag, Au, Cu, diamond, high-temperature sintered graphite and beryllia,(B) at least one metal filler selected from the group consisting of Al, Fe and Mg,(C) a polyimide resin having an imidization degree of 80% or more, obtained by reacting 3,3',4,4'-benzophenonetetracarboxylic acid dianhydride or 3,3',4,4'-oxydiphthalic acid dianhydride with a diamine, and(D) an organic solvent, wherein the weight proportions of (A), (B) and (C) are(A)/[(B)+(C)]=10/90 to 90/10(B)/[(A)+(C)]=5/95 to 90/10and the weight proportion of (D) is(D)/[(A)+(B)+(C)]=0.01/100 to 50/100.Type: GrantFiled: September 9, 1992Date of Patent: February 8, 1994Assignees: Sumitomo Bakelite Company Limited, NEC CorporationInventors: Sueo Morishige, Kenichi Kaneda, Katsushi Terajima, Toshiro Takeda, Yushi Sakamoto, Takashi Suzuki
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Patent number: 5087963Abstract: In a glass-sealed semiconductor device, low-melting glass is glazed on a ceramic base to fix a lead frame. A distal end portion of the lead frame, the distal end portion being connected to a semiconductor element, is fixed to the ceramic base through devitrifying glass layer.Type: GrantFiled: October 12, 1990Date of Patent: February 11, 1992Assignee: NEC CorporationInventors: Kenichi Kaneda, Akio Tanda