Patents by Inventor Kenichi Kitamura

Kenichi Kitamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11912679
    Abstract: [Problem] A compound which is useful as a STING inhibitor is provided. [Means for Solution] The present inventors have found aryl alkynamide derivatives having an inhibitory action on STING. The aryl alkynamide derivatives of the present invention have an inhibitory action on STING and can be used as an agent for treating an autoimmune disease, a neurodegenerative disease, a type I interferonopathy and/or other STING-mediated disease.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: February 27, 2024
    Assignees: Astellas Pharma, Inc., Mitobridge, Inc.
    Inventors: Junko Maeda, Ikumi Kuriwaki, Kai Kitamura, Yumi Yamashita, Kenichi Kakefuda, Akio Kamikawa, Kenji Negoro, Wataru Hamaguchi, Ryushi Seo, Jeffrey Ciavarri
  • Patent number: 11718095
    Abstract: A flow channel member includes a first flow channel member non-transmissive of ultraviolet light and absorbent of laser light, a second flow channel member non-transmissive of ultraviolet light and absorbent of laser light, the second flow channel member being stacked on the first flow channel member to define a flow channel for liquid to flow between the second flow channel member and the first flow channel member, and a third flow channel member transmissive of laser light, the third flow channel member being fixed to the first flow channel member and the second flow channel member in such a manner as to close a gap between the first flow channel member and the second flow channel member.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: August 8, 2023
    Assignee: Seiko Epson Corporation
    Inventors: Ken Yamagishi, Shigeki Suzuki, Kenichi Kitamura
  • Publication number: 20220203684
    Abstract: A flow channel member includes a first flow channel member non-transmissive of ultraviolet light and absorbent of laser light, a second flow channel member non-transmissive of ultraviolet light and absorbent of laser light, the second flow channel member being stacked on the first flow channel member to define a flow channel for liquid to flow between the second flow channel member and the first flow channel member, and a third flow channel member transmissive of laser light, the third flow channel member being fixed to the first flow channel member and the second flow channel member in such a manner as to close a gap between the first flow channel member and the second flow channel member.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 30, 2022
    Inventors: Ken YAMAGISHI, Shigeki SUZUKI, Kenichi KITAMURA
  • Patent number: 11047112
    Abstract: A control system includes: an engine; a first hydraulic pump and a second hydraulic pump driven by the engine; a switching device provided in a flow path that connects the first hydraulic pump to the second hydraulic pump, and configured to perform switching between a merged state in which the flow path is opened and a separated state in which the flow path is closed; a first hydraulic actuator to which hydraulic fluid discharged from the first hydraulic pump is supplied in the separated state; a second hydraulic actuator to which hydraulic fluid discharged from the second hydraulic pump is supplied in the separated state; a determining unit configured to determine whether output of the engine is limited; and a merging-separating control unit configured to control the switching device so as to perform switching to the merged state when the determining unit determines that output of the engine is limited.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 29, 2021
    Assignee: Komatsu Ltd.
    Inventors: Shimon Jimbo, Kenichi Kitamura, Yoshihiro Kumagae
  • Patent number: 10824395
    Abstract: An arithmetic processing device includes a coefficient memory storing coefficients of a Taylor series expansion of a trigonometric function, a multiply-add arithmetic unit, a first bypass path supplying an output of the multiply-add arithmetic unit to a register file, an OR circuit calculating OR of a sign bit of the output of the multiply-add arithmetic unit and a least significant bit of a second input, a first selector selecting either a first input y or a value “1.0” an EOR circuit calculating an EOR of a first bit of the second input and a sign bit of an output of the first selector, and a second bypass path supplying the least significant bit of the second input to a coefficient selector. The multiply-add arithmetic unit executes an auxiliary instruction repeatedly while modifying a coefficient index from a maximum value to a minimum value to calculate sin (x).
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: November 3, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Kenichi Kitamura
  • Patent number: 10579333
    Abstract: An arithmetic unit includes a multiplier multiplying first and second inputs to output a multiplication result, an adder adding the third input to the multiplication result to output a multiplication addition result, a normalization shift circuit shifting the multiplication addition result left with a left shift amount, and a left shift amount prediction circuit. The adder includes a carry-save adder adding a first addition value and a first carry value to the third input and a full adder outputting the multiplication addition result. The left shift amount prediction circuit includes a leading zero count circuit generating a leading zero count, a leading one count circuit generating a leading one count, and a correction circuit correcting the leading one count to zero when NOR of respective least significant bits of the M upper order bits of the second addition value and the second carry value of the full adder is true.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: March 3, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Kenichi Kitamura
  • Patent number: 10496540
    Abstract: A processor includes a cache memory, an issuing unit that issues, with respect to all element data as a processing object of a load instruction, a cache request to the cache memory for each of a plurality of groups which are divided to include element data, a comparing unit that compares addresses of the element data as the processing object of the load instruction, and determines whether element data in a same group are simultaneously accessible, and a control unit that accesses the cache memory according to the cache request registered in a load queue registering one or more cache requests issued from the issuing unit. The control unit processes by one access whole element data determined to be simultaneously accessible by the comparing unit.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: December 3, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Hideki Okawara, Noriko Takagi, Yasunobu Akizuki, Kenichi Kitamura, Mikio Hondo
  • Patent number: 10473630
    Abstract: A preprocessing kit includes a separation device, a collecting container, and a skirt part. The skirt part is integrated with the separation device, and is provided to surround an outer circumferential surface of the separation device with a clearance being left from the outer circumferential surface so that a space having a closed upper side and an open lower side is formed between the outer circumferential surface of the separation device and the skirt part. The skirt part is provided in such a way that a lower end of the skirt part comes into intimate contact with a peripheral surface of an opening of the recess part when the collecting container containing the lower end of the separation device is fitted into the recess part.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: November 12, 2019
    Assignee: SHIMADZU CORPORATION
    Inventors: Nobuhiro Hanafusa, Kenichi Kitamura
  • Publication number: 20190227771
    Abstract: An arithmetic processing device includes a coefficient memory storing coefficients of a Taylor series expansion of a trigonometric function, a multiply-add arithmetic unit, a first bypass path supplying an output of the multiply-add arithmetic unit to a register file, an OR circuit calculating OR of a sign bit of the output of the multiply-add arithmetic unit and a least significant bit of a second input, a first selector selecting either a first input y or a value “1.0” an EOR circuit calculating an EOR of a first bit of the second input and a sign bit of an output of the first selector, and a second bypass path supplying the least significant bit of the second input to a coefficient selector. The multiply-add arithmetic unit executes an auxiliary instruction repeatedly while modifying a coefficient index from a maximum value to a minimum value to calculate sin (x).
    Type: Application
    Filed: January 9, 2019
    Publication date: July 25, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Kenichi Kitamura
  • Publication number: 20190032306
    Abstract: A control system includes: an engine; a first hydraulic pump and a second hydraulic pump driven by the engine; a switching device provided in a flow path that connects the first hydraulic pump to the second hydraulic pump, and configured to perform switching between a merged state in which the flow path is opened and a separated state in which the flow path is closed; a first hydraulic actuator to which hydraulic fluid discharged from the first hydraulic pump is supplied in the separated state; a second hydraulic actuator to which hydraulic fluid discharged from the second hydraulic pump is supplied in the separated state; a determining unit configured to determine whether output of the engine is limited; and a merging-separating control unit configured to control the switching device so as to perform switching to the merged state when the determining unit determines that output of the engine is limited.
    Type: Application
    Filed: July 27, 2017
    Publication date: January 31, 2019
    Inventors: Shimon Jimbo, Kenichi Kitamura, Yoshihiro Kumagae
  • Publication number: 20180336013
    Abstract: An arithmetic unit includes a multiplier multiplying first and second inputs to output a multiplication result, an adder adding the third input to the multiplication result to output a multiplication addition result, a normalization shift circuit shifting the multiplication addition result left with a left shift amount, and a left shift amount prediction circuit. The adder includes a carry-save adder adding a first addition value and a first carry value to the third input and a full adder outputting the multiplication addition result. The left shift amount prediction circuit includes a leading zero count circuit generating a leading zero count, a leading one count circuit generating a leading one count, and a correction circuit correcting the leading one count to zero when NOR of respective least significant bits of the M upper order bits of the second addition value and the second carry value of the full adder is true.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 22, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Kenichi Kitamura
  • Publication number: 20180336028
    Abstract: A processing device includes an instruction control unit configured to issue an instruction, an operation unit configured to perform a floating-point operation in accordance with an instruction issued from the instruction control unit, a detection unit configured to detect a subnormal number from data related to the floating-point operation performed in the operation unit, and a processing unit configured to process the data in a case in which a subnormal number is included in the data. When committing the instruction, in a case in which a subnormal number was detected by the detection unit from the data related to the floating-point operation performed in accordance with the instruction, the instruction control unit transits to a subnormal processing mode for processing a subnormal number, instructs the operation unit to re-execute the instruction, and instructs the processing unit to process the detected subnormal number.
    Type: Application
    Filed: May 15, 2018
    Publication date: November 22, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Yuhei TAKATA, Kenichi KITAMURA
  • Publication number: 20170217197
    Abstract: A flow-path structure configures an internal flow path for supply a liquid to a nozzle which ejects the liquid, and the flow-path structure includes a filter disposed across the internal flow path; a defoaming space that communicates with a defoaming route through which gases are discharged; and a first gas permeable membrane that is interposed between the defoaming space and a storage space positioned on a downstream side from the filter.
    Type: Application
    Filed: January 31, 2017
    Publication date: August 3, 2017
    Inventors: Takahiro KANEGAE, Masahiko SATO, Kenichi KITAMURA, Shigeki SUZUKI, Ken YAMAGISHI
  • Publication number: 20170168027
    Abstract: A preprocessing kit includes a separation device, a collecting container, and a skirt part. The skirt part is integrated with the separation device, and is provided to surround an outer circumferential surface of the separation device with a clearance being left from the outer circumferential surface so that a space having a closed upper side and an open lower side is formed between the outer circumferential surface of the separation device and the skirt part. The skirt part is provided in such a way that a lower end of the skirt part comes into intimate contact with a peripheral surface of an opening of the recess part when the collecting container containing the lower end of the separation device is fitted into the recess part.
    Type: Application
    Filed: September 2, 2014
    Publication date: June 15, 2017
    Applicant: SHIMADZU CORPORATION
    Inventors: Nobuhiro HANAFUSA, Kenichi KITAMURA
  • Patent number: 9605410
    Abstract: A hybrid hydraulic excavator includes an engine, a generator motor, a capacitor, a cooling system being configured to cool the capacitor, and a controller. The cooling system includes a circulation mechanism being configured to circulate a cooling water, and a cooler being configured to cool the cooling water with output from the engine. The controller prohibits auto-stop of the engine when it is determined that the capacitor is overheated.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: March 28, 2017
    Inventor: Kenichi Kitamura
  • Publication number: 20170060748
    Abstract: A processor includes a cache memory, an issuing unit that issues, with respect to all element data as a processing object of a load instruction, a cache request to the cache memory for each of a plurality of groups which are divided to include element data, a comparing unit that compares addresses of the element data as the processing object of the load instruction, and determines whether element data in a same group are simultaneously accessible, and a control unit that accesses the cache memory according to the cache request registered in a load queue registering one or more cache requests issued from the issuing unit. The control unit processes by one access whole element data determined to be simultaneously accessible by the comparing unit.
    Type: Application
    Filed: July 27, 2016
    Publication date: March 2, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Hideki Okawara, Noriko Takagi, YASUNOBU AKIZUKI, Kenichi Kitamura, Mikio Hondo
  • Patent number: 9145658
    Abstract: A hybrid hydraulic excavator includes: an engine; a generator motor; an electric storage device; a commanding system being configured to command at least activation of a service mode for maintenance and execution of a charge-release process for the electric storage device; a display being configured to provide at least information on the charge-release process for the electric storage device; and a display controller being configured to control displaying of the display. The display controller commands the display to display charge-release-failure information when the charge-release process is ongoing at the elapse of a predetermined duration of time since the activation of the service mode was commanded.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: September 29, 2015
    Assignee: Komatsu Ltd.
    Inventors: Kenichi Kitamura, Kentaro Murakami
  • Patent number: 9009209
    Abstract: A processor for dividing by calculating repeatedly an n-bit width partial quotient includes, a dividend zero count value counter that counts a dividend zero count value, a divisor zero count value counter that counts a divisor zero count value, a correction value calculator that calculates a correction value to a loop count value, a correction loop count value calculator that calculates a correction loop count value, a dividend shift unit that shifts leftward an absolute value of the dividend by the dividend zero count value and shifts rightward the leftward-shifted absolute value of the dividend by the correction value, a divisor shift unit that shifts leftward an absolute value of the divisor by the divisor zero count value, and a division loop operation unit that divides based on an output value from the dividend shift unit, an output value from the divisor shift unit, and the correction loop count value.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: April 14, 2015
    Assignee: Fujitsu Limited
    Inventors: Kenichi Kitamura, Shiro Kamoshida
  • Publication number: 20150046004
    Abstract: A hybrid hydraulic excavator includes: an engine; a generator motor; an electric storage device; a commanding system being configured to command at least activation of a service mode for maintenance and execution of a charge-release process for the electric storage device; a display being configured to provide at least information on the charge-release process for the electric storage device; and a display controller being configured to control displaying of the display. The display controller commands the display to display charge-release-failure information when the charge-release process is ongoing at the elapse of a predetermined duration of time since the activation of the service mode was commanded.
    Type: Application
    Filed: July 23, 2013
    Publication date: February 12, 2015
    Applicant: Komatsu Ltd.
    Inventors: Kenichi Kitamura, Kentaro Murakami
  • Patent number: PP25409
    Abstract: A new and distinct cultivar of Mandevilla plant named ‘Sunparakitaho’, characterized by its upright and vining plant habit; vigorous growth habit; freely branching habit, dense and bushy plant form; glossy dark green-colored leaves; freely flowering habit; long flowering period; and medium-sized flowers with pale pink-colored flowers with yellow orange-colored throats.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: April 7, 2015
    Assignee: Suntory Flowers Ltd.
    Inventor: Kenichi Kitamura