Patents by Inventor Kenichi Kuroda

Kenichi Kuroda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140023410
    Abstract: A developing roller is provided which is capable of forming a toner layer having the most uniform possible thickness on an outer peripheral surface of a roller body thereof. The roller body (2) of the developing roller (1) is formed from a rubber composition containing a base rubber which is a mixture of NBR and/or SBR, CR, an epichlorohydrin rubber and IIR, wherein the IIR is present in a proportion of not less than 2.5 parts by mass and not greater than 20 parts by mass in 100 parts by mass of the base rubber.
    Type: Application
    Filed: June 17, 2013
    Publication date: January 23, 2014
    Inventors: Akihiko KAWATANI, Kenichi KURODA
  • Patent number: 8604505
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: December 10, 2013
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Patent number: 8569123
    Abstract: An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer 2; (c) removing a surface layer of the silicon carbide layer 2, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: October 29, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Matsuno, Kenichi Ohtsuka, Naoki Yutani, Kenichi Kuroda, Hiroshi Watanabe, Shozo Shikama
  • Publication number: 20130241029
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: April 8, 2013
    Publication date: September 19, 2013
    Applicants: HITACHI ULSI SYSTEMS CO., LTD., RENESAS ELECTRONICS CORPORATION
    Inventors: Kenichi KURODA, Kozo WATANABE, Hirohiko YAMAMOTO
  • Patent number: 8426969
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: April 23, 2013
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Publication number: 20130089362
    Abstract: A developing roller is provided, which is particularly used in an image forming apparatus of a highly durable design and is free from toner leakage even after formation of a predetermined number of images. Opposite end regions (5a) of an outer peripheral surface (5) of a roller body (2) of the developing roller (1) to be respectively kept in sliding contact with seal members each have a friction coefficient ? of not greater than 0.15.
    Type: Application
    Filed: July 27, 2012
    Publication date: April 11, 2013
    Inventors: Kenichi KURODA, Akihiko Kawatani, Masakazu Tanaka, Yoshihisa Mizumoto
  • Publication number: 20130051870
    Abstract: An inventive developing roller is adapted for use in an electrophotographic image forming apparatus. The developing roller includes a roller body. At least an outer peripheral surface of the roller body is formed from a rubber composition containing a base rubber. The base rubber contains a styrene butadiene rubber in a proportion of not less than 10 mass % and not greater than 70 mass % based on the overall amount of the base rubber. The outer peripheral surface of the rubber body has a surface roughness Ra of not less than 0.78 ?m and not greater than 1.8 ?m.
    Type: Application
    Filed: June 12, 2012
    Publication date: February 28, 2013
    Inventors: Kenichi KURODA, Akihiko Kawatani, Yoshihisa Mizumoto
  • Patent number: 8377811
    Abstract: An object of the invention is to provide a method for manufacturing a silicon carbide semiconductor device having constant characteristics with reduced variations in forward characteristics. The method for manufacturing the silicon carbide semiconductor device according to the invention includes the steps of: (a) preparing a silicon carbide substrate; (b) forming an epitaxial layer on a first main surface of the silicon carbide substrate; (c) forming a protective film on the epitaxial layer; (d) forming a first metal layer on a second main surface of the silicon carbide substrate; (e) applying heat treatment to the silicon carbide substrate at a predetermined temperature to form an ohmic junction between the first metal layer and the second main surface of the silicon carbide substrate; (f) removing the protective film; (g) forming a second metal layer on the epitaxial layer; and (h) applying heat treatment to the silicon carbide substrate at a temperature from 400° C. to 600° C.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: February 19, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Matsuno, Kenichi Ohtsuka, Kenichi Kuroda, Shozo Shikama, Naoki Yutani
  • Publication number: 20120308622
    Abstract: Compositions of apatite derivative crystals are disclosed herein. Also disclosed are methods of using these compositions to treat tooth sensitivity, to use as an anticaries treatment, to use as a restorative material, to use as a tooth surface whitener, and to combat or lessen the side effects of tooth whitening.
    Type: Application
    Filed: November 8, 2010
    Publication date: December 6, 2012
    Applicant: The Regents Of The University Of Michigan
    Inventors: Brian H. Clarkson, Kenichi Kuroda
  • Patent number: 8304901
    Abstract: In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: November 6, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroshi Watanabe, Naoki Yutani, Kenichi Ohtsuka, Kenichi Kuroda, Masayuki Imaizumi, Yoshinori Matsuno
  • Publication number: 20120241766
    Abstract: A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).
    Type: Application
    Filed: December 27, 2010
    Publication date: September 27, 2012
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenichi Ohtsuka, Kenichi Kuroda, Hiroshi Watanabe, Naoki Yutani, Hiroaki Sumitani
  • Publication number: 20120126360
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: January 31, 2012
    Publication date: May 24, 2012
    Inventors: Kenichi KURODA, Kozo Watanabe, Hirohiko Yamamoto
  • Patent number: 8119495
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: February 21, 2012
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Publication number: 20120028453
    Abstract: An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer 2; (c) removing a surface layer of the silicon carbide layer 2, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching.
    Type: Application
    Filed: September 1, 2009
    Publication date: February 2, 2012
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yoshinori Matsuno, Kenichi Ohtsuka, Naoki Yutani, Kenichi Kuroda, Hiroshi Watanabe, Shozo Shikama
  • Publication number: 20120014723
    Abstract: The semiconductive roller according to the present invention includes a roller body having an outer peripheral surface made of a crosslinked substance of a semiconductive rubber composition and exhibiting Shore A hardness of not more than 60, the semiconductive rubber composition contains a base polymer made of a mixture of (1) mixed rubber N of liquid nitrile rubber and solid nitrile rubber, (2) chloroprene rubber C, and (3) epichlorohydrin rubber E in a mass ratio (C+E)/N of 10/90 to 80/20, the ratios of the chloroprene rubber and the epichlorohydrin rubber in the total quantity of the base polymer are not less than 5 mass % and not less than 5 mass % respectively, and roller resistance at an applied voltage of 5 V is not less than 104? and not more than 109?.
    Type: Application
    Filed: July 1, 2011
    Publication date: January 19, 2012
    Inventors: Yoshihisa MIZUMOTO, Akihiko KAWATANI, Takashi MARUI, Kenichi KURODA
  • Publication number: 20110207288
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Application
    Filed: April 28, 2011
    Publication date: August 25, 2011
    Inventors: Kenichi KURODA, Kozo Watanabe, Hirohiko Yamamoto
  • Patent number: 7965563
    Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: June 21, 2011
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kiyoshi Matsubara, Naoki Yashiki, Shiro Baba, Takashi Ito, Hirofumi Mukai, Masanao Sato, Masaaki Terasawa, Kenichi Kuroda, Kazuyoshi Shiba
  • Patent number: 7948086
    Abstract: There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: May 24, 2011
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kenichi Kuroda, Kozo Watanabe, Hirohiko Yamamoto
  • Publication number: 20110001209
    Abstract: In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage.
    Type: Application
    Filed: March 12, 2009
    Publication date: January 6, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroshi Watanabe, Naoki Yutani, Kenichi Ohtsuka, Kenichi Kuroda, Masayuki Imaizumi, Yoshinori Matsuno
  • Patent number: 7847296
    Abstract: On a major surface of an n-type silicon carbide inclined substrate (2) is formed an n-type voltage-blocking layer (3) made of silicon carbide by means of epitaxial growth. On the n-type voltage-blocking layer (3) is formed a p-type silicon carbide region (4) rectangular when viewed from above. On the surface of the p-type silicon carbide region (4) is formed a p-type contact electrode (5). In the p-type silicon carbide region (4), the periphery of the p-type silicon carbide region (4) that is parallel with a (11-20) plane (14a) of the silicon carbide crystal, which is liable to cause avalanche breakdown, is located on the short side. In this manner, the dielectric strength of a silicon carbide semiconductor device can be improved.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: December 7, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiroshi Sugimoto, Yoshinori Matsuno, Kenichi Ohtsuka, Noboru Mikami, Kenichi Kuroda