Patents by Inventor Kenichi Kusumoto
Kenichi Kusumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240107865Abstract: Manufacturing equipment for a light-emitting device with which steps from formation to sealing of a light-emitting element can be successively performed is provided. With the manufacturing equipment for a light-emitting device, a deposition step, a lithography step, and an etching step for forming an organic EL element and a sealing step by formation of a protective layer can be successively performed. Accordingly, a downscaled organic EL element with high luminance and high reliability can be formed. Moreover, the manufacturing equipment can have an in-line system where apparatuses are arranged in the order of process steps for the light-emitting device, resulting in high throughput manufacturing.Type: ApplicationFiled: January 28, 2022Publication date: March 28, 2024Inventors: Shingo EGUCHI, Hiroki ADACHI, Kenichi OKAZAKI, Yasumasa YAMANE, Naoto KUSUMOTO, Kensuke YOSHIZUMI, Shunpei YAMAZAKI
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Publication number: 20230209809Abstract: Apparatuses and methods for fabricating multilayer structures are described. An example method includes: forming a conductive base layer including silicon; forming a first conductive layer including first conductive material above the conductive base layer; forming a conductive barrier layer above the conductive layer; performing thermal loading to form a second conductive layer including silicide of the first conductive material between the conductive base layer and the conductive barrier layer; and forming a third conductive layer above the conductive barrier layer.Type: ApplicationFiled: March 7, 2022Publication date: June 29, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: AKIE SHIMAMURA, KENICHI KUSUMOTO
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Publication number: 20210296167Abstract: Microelectronic devices—having at least one conductive contact structure adjacent a silicide region—are formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).Type: ApplicationFiled: June 7, 2021Publication date: September 23, 2021Inventors: Kenichi Kusumoto, Taizo Yasuda, Hidekazu Nobuto, Kohei Morita
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Conductive line construction, memory circuitry, and method of forming a conductive line construction
Patent number: 11075274Abstract: A method of forming a conductive line construction comprises forming a structure comprising polysilicon-comprising material. Elemental titanium is directly against the polysilicon of the polysilicon-comprising material. Silicon nitride is directly against the elemental titanium. Elemental tungsten is directly against the silicon nitride. The structure is annealed to form a conductive line construction comprising the polysilicon-comprising material, titanium silicide directly against the polysilicon-comprising material, elemental tungsten, TiSixNy between the elemental tungsten and the titanium silicide, and one of (a) or (b), with (a) being the TiSixNy is directly against the titanium silicide, and (b) being titanium nitride is between the TiSixNy and the titanium silicide, with the TiSixNy being directly against the titanium nitride and the titanium nitride being directly against the titanium silicide. Structure independent of method is disclosed.Type: GrantFiled: January 18, 2019Date of Patent: July 27, 2021Assignee: Micron Technology, Inc.Inventors: Kenichi Kusumoto, Yasutaka Iuchi, Akie Shimamura -
Patent number: 11043414Abstract: Microelectronic devices—having at least one conductive contact structure adjacent a silicide region—are formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).Type: GrantFiled: October 16, 2019Date of Patent: June 22, 2021Assignee: Micron Technology, Inc.Inventors: Kenichi Kusumoto, Taizo Yasuda, Hidekazu Nobuto, Kohei Morita
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Publication number: 20210118676Abstract: Microelectronic devices—having at least one conductive contact structure adjacent a silicide region—are formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).Type: ApplicationFiled: October 16, 2019Publication date: April 22, 2021Inventors: Kenichi Kusumoto, Taizo Yasuda, Hidekazu Nobuto, Kohei Morita
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Conductive Line Construction, Memory Circuitry, And Method Of Forming A Conductive Line Construction
Publication number: 20200235219Abstract: A method of forming a conductive line construction comprises forming a structure comprising polysilicon-comprising material. Elemental titanium is directly against the polysilicon of the polysilicon-comprising material. Silicon nitride is directly against the elemental titanium. Elemental tungsten is directly against the silicon nitride. The structure is annealed to form a conductive line construction comprising the polysilicon-comprising material, titanium silicide directly against the polysilicon-comprising material, elemental tungsten, TiSixNy between the elemental tungsten and the titanium silicide, and one of (a) or (b), with (a) being the TiSixNy is directly against the titanium silicide, and (b) being titanium nitride is between the TiSixNy and the titanium silicide, with the TiSixNy being directly against the titanium nitride and the titanium nitride being directly against the titanium silicide. Structure independent of method is disclosed.Type: ApplicationFiled: January 18, 2019Publication date: July 23, 2020Applicant: Micron Technology, Inc.Inventors: Kenichi Kusumoto, Yasutaka Iuchi, Akie Shimamura -
Patent number: 10438954Abstract: A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride layer on the tungsten layer in the second chamber.Type: GrantFiled: September 18, 2018Date of Patent: October 8, 2019Assignee: Micron Technology, Inc.Inventors: Kenichi Kusumoto, Yasutaka Iuchi
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Publication number: 20190035793Abstract: A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride layer on the tungsten layer in the second chamber.Type: ApplicationFiled: September 18, 2018Publication date: January 31, 2019Applicant: Micron Technology, Inc.Inventors: Kenichi Kusumoto, Yasutaka Iuchi
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Patent number: 10109635Abstract: A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride layer on the tungsten layer in the second chamber.Type: GrantFiled: May 11, 2017Date of Patent: October 23, 2018Assignee: Micron Technology, Inc.Inventors: Kenichi Kusumoto, Yasutaka Iuchi
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Publication number: 20180083010Abstract: A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride layer on the tungsten layer in the second chamber.Type: ApplicationFiled: May 11, 2017Publication date: March 22, 2018Inventors: Kenichi Kusumoto, Yasutaka Iuchi
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Patent number: 8299129Abstract: The present invention provides a carrier capable of highly efficiently introducing a compound into cells with low cytotoxicity, which contains peptide lipids represented by the following formula, and a method for introducing a compound into cells using the carrier: wherein R1 is an amino acid or peptide having 1-10 amino acid residues, R2 is a side chain of any amino acid, provided that R2 has a carboxyl group, the carboxyl group may be an ester with a hydrocarbon group having 1-30 carbon atoms, R3 is a hydrocarbon group having 1-30 carbon atoms.Type: GrantFiled: March 1, 2006Date of Patent: October 30, 2012Assignees: Fukuoka Prefectural Government, Kyoto University, Dojindo LaboratoriesInventors: Kenichi Kusumoto, Itaru Hamachi, Kazumi Sasamoto, Tetsuyuki Akao, Munetaka Ishiyama, Takahiro Nagata, Chizu Ikeda, Takeshi Ido, Satoko Yamashita, Rieko Kuroda, Tomoyuki Ishikawa
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Publication number: 20090170960Abstract: The present invention provides a carrier capable of highly efficiently introducing a compound into cells with low cytotoxicity, which contains peptide lipids represented by the following formula, and a method for introducing a compound into cells using the carrier: wherein R1 is an amino acid or peptide having 1-10 amino acid residues, R2 is a side chain of any amino acid, provided that R2 has a carboxyl group, the carboxyl group may be an ester with a hydrocarbon group having 1-30 carbon atoms, R3 is a hydrocarbon group having 1-30 carbon atoms.Type: ApplicationFiled: March 1, 2006Publication date: July 2, 2009Applicants: FUKUOKA PREFECTURAL GOVERNMENT, KYOTO UNIVERSITY, DOJINDO LABORATORIESInventors: Kenichi Kusumoto, Itaru Hamachi, Kazumi Sasamoto, Tetsuyuki Akao, Munetaka Ishiyama, Takahiro Nagata, Chizu Ikeda, Takeshi Ido, Satoko Yamashita, Rieko Kuroda, Tomoyuki Ishikawa
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Publication number: 20090065779Abstract: A semiconductor device includes a silicon substrate; a gate insulation film formed on the silicon substrate; and a gate electrode formed on the gate insulation film; wherein the gate electrode has a first doped polysilicon film formed on the gate insulation film, and a second doped polysilicon film formed on the first doped polysilicon film; wherein the first doped polysilicon film includes first impurities; and wherein the second doped polysilicon film includes second impurities that has the opposite conductivity type from the first impurities.Type: ApplicationFiled: September 9, 2008Publication date: March 12, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Kenichi KUSUMOTO
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Patent number: 5268141Abstract: An iron base alloy is disclosed which consists essentially of 0.005%-7.0% of aluminum, 0.005-7.0% of silicon, 0.0001%-0.005% of magnesium, 0.0001-0.005% of calcium, 0.001%-0.002% of oxygen, 0.0001-0.002% of sulphur, and 0.0005%-0.003% of nitrogen, less than 2% of carbon, minor amounts of phosphorous and manganese and the remainder iron.Type: GrantFiled: May 15, 1991Date of Patent: December 7, 1993Assignees: Mitsui Engineering and Ship Building Co., Ltd., Metal Research CorporationInventors: Tohei Ototani, Toru Degawa, Kenichi Kusumoto, Makoto Ebata
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Patent number: 4820485Abstract: A method of producing an alloy containing at least one major ingredient selected from the group consisting of iron (Fe), cobalt (Co), and Nickel (Ni) and having low contents of sulphur, oxygen, and nitrogen, comprises steps of:(a) holding a molten alloy in a container selected from the group consisting of a lime crucible, a lime crucible furnace, a converter and a ladle lined with a basic refractory consisting of 15-85% of calcium oxide (CaO), and 15-75% of magnesium oxide (MgO), wherein said alloy consists essentially of at least one major ingredient selected from the group consisting of iron (Fe), nickel (Ni), and cobalt (Co);(b) adding at least one additive, based on the molten alloy, into said molten alloy in an atmosphere selected from the group consisting of a non-oxidizing atmosphere and a vacuum, wherein said additive is selected from the group consisting of aluminum (Al), aluminum alloys, silicon and silicon alloys;(c) desulphurizing, deoxidizing and denitrifying said molten alloy under an atmosphereType: GrantFiled: February 3, 1987Date of Patent: April 11, 1989Assignees: Mitsui Engineering and Ship Building Co., Ltd., Metal Research CorporationInventors: Tohei Ototani, Toru Degawa, Kenichi Kusumoto, Makoto Ebata
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Patent number: 4729787Abstract: A method of producing an alloy containing at least one major ingredient selected from the group consisting of iron (Fe), cobalt (Co), and Nickel (Ni) and having low contents of sulphur, oxygen, and nitrogen, comprises steps of:(a) holding a molten alloy in a container selected from the group consisting of a lime crucible, a lime crucible furnace, a converter and a ladle lined with a basic refractory consisting of 15-85% of calcium oxide (CaO), and 15-75% of magnesium oxide (MgO), wherein said alloy consists essentially of at least one major ingredient selected from the group consisting of iron (Fe), nickel (Ni), and cobalt (Co);(b) adding at least one additive, based on the molten alloy, into said molten alloy in an atmosphere selected from the group consisting of a non-oxidizing atmosphere and a vacuum, wherein said additive is selected from the group consisting of aluminum (Al), aluminum alloys, silicon and silicon alloys;(c) desulphurizing, deoxidizing and denitrifying said molten alloy under an atmosphereType: GrantFiled: December 3, 1986Date of Patent: March 8, 1988Assignees: Mitsui Engineering and Ship Building Co., Ltd., Metal Research CorporationInventors: Tohei Ototani, Toru Degawa, Kenichi Kusumoto, Makoto Ebata