Patents by Inventor Kenichi Maki

Kenichi Maki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11652178
    Abstract: The finger electrode is formed by hard-soldered silver paste. The melting point of the first type solder layer provided on the surface of the terminal wiring member is higher than the melting point of the second type solder layer provided on the surface of the wire. The first width, in the first direction, of the second type solder layer in the first portion where the wire is connected to the terminal wiring member is larger than the second width, in the first direction, of the second type solder layer in the second portion where the wire is connected to the finger electrode.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: May 16, 2023
    Assignee: PANASONIC HOLDINGS CORPORATION
    Inventors: Haruhisa Hashimoto, Kenichi Maki
  • Publication number: 20230089218
    Abstract: This method for manufacturing a solar cell module comprises a step for applying an adhesive to a first adhesion region so that the first adhesion region and a second adhesion region are disposed alternately on a light receiving surface of a solar cell along a first direction, and a step for arranging a light receiving surface-side wiring material along the first direction on the light receiving surface side of the solar cell to which the adhesive has been applied. The step for arranging the light receiving surface-side wiring material comprises arranging the light receiving surface-side wiring material, in the first adhesion region and the second adhesion region of the solar cell so that, in a state in which a first holder is in contact with the holding region of the light receiving surface-side wiring material, the second adhesion region and the holding region overlap each other.
    Type: Application
    Filed: February 5, 2021
    Publication date: March 23, 2023
    Inventors: Kenichi MAKI, Haruhisa HASHIMOTO, Koutarou SUMITOMO, Hiroshi KANNO
  • Patent number: 11581455
    Abstract: First, first cell wiring members from the first solar cell and second cell wiring members from the second solar cell are sandwiched between a wiring member film and a second bridge wiring member. Subsequently, the first cell wiring members and the second cell wiring members are connected to the second bridge wiring member by applying heat to at least the first cell wiring members, the second cell wiring members, and the second bridge wiring member by induction heating.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: February 14, 2023
    Assignee: PANASONIC HOLDINGS CORPORATION
    Inventors: Kenichi Maki, Haruhisa Hashimoto, Naoto Imada
  • Publication number: 20220005969
    Abstract: First, first cell wiring members from the first solar cell and second cell wiring members from the second solar cell are sandwiched between a wiring member film and a second bridge wiring member. Subsequently, the first cell wiring members and the second cell wiring members are connected to the second bridge wiring member by applying heat to at least the first cell wiring members, the second cell wiring members, and the second bridge wiring member by induction heating.
    Type: Application
    Filed: August 23, 2019
    Publication date: January 6, 2022
    Inventors: Kenichi MAKI, Haruhisa HASHIMOTO, Naoto IMADA
  • Publication number: 20200212233
    Abstract: The finger electrode is formed by hard-soldered silver paste. The melting point of the first type solder layer provided on the surface of the terminal wiring member is higher than the melting point of the second type solder layer provided on the surface of the wire. The first width, in the first direction, of the second type solder layer in the first portion where the wire is connected to the terminal wiring member is larger than the second width, in the first direction, of the second type solder layer in the second portion where the wire is connected to the finger electrode.
    Type: Application
    Filed: December 23, 2019
    Publication date: July 2, 2020
    Inventors: Haruhisa HASHIMOTO, Kenichi MAKI
  • Publication number: 20200194606
    Abstract: A solar cell module includes a plurality of solar cells arranged to be aligned along a first direction, a plurality of wiring materials configured to connect the plurality of solar cells, a plurality of first transparent members disposed individually on respective light receiving surface sides of the plurality of solar cells and bonded to the plurality of wiring materials, and a plurality of second transparent members disposed individually on respective rear surface sides of the plurality of solar cells, the rear surface sides being opposite to the light receiving surface sides, and bonded to the plurality of wiring materials.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 18, 2020
    Applicant: Panasonic Corporation
    Inventors: Yuya Nakamura, Haruhisa Hashimoto, Junpei Irikawa, Naoto Imada, Kenichi Maki, Takeshi Nishiwaki, Hitomi Ichinose
  • Publication number: 20200105954
    Abstract: The second bridge wiring member includes a surface having a length in the first direction and a width in the second direction. A plurality of first cell wiring members extending from the 1-8th solar cell toward the second bridge wiring member and a plurality of second cell wiring members extending from the 2-8th solar cell toward the second bridge wiring member are connected to the surface of the second bridge wiring member such that the plurality of first cell wiring members and the plurality of second cell wiring members mutually overlap along the second direction.
    Type: Application
    Filed: September 4, 2019
    Publication date: April 2, 2020
    Inventors: Kenichi MAKI, Haruhisa HASHIMOTO, Naoto IMADA
  • Patent number: 9373738
    Abstract: Provided is a solar module with improved reliability. A solar module (1) is provided with a solar cell (10), a wiring member (11), a resin adhesive layer (12), and a buffer region (40). The wiring member (11) is electrically connected to the solar cell (10). The resin adhesive layer (12) bonds the solar cell (10) and the wiring member (11) to one another. The buffer region (40) is provided at least partially between the wiring member (11) and the solar cell (10). The buffer region (40) contains a non-crosslinked resin.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: June 21, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Kenichi Maki, Haruhisa Hashimoto
  • Publication number: 20150194924
    Abstract: A solar cell module wherein fluctuations of output characteristics are unlikely to occur is provided. This solar cell module includes a solar cell, a first protective member provided on an outer side of the solar cell when viewed from the moving body, a second protective member provided on an inner side of the solar cell when viewed from the moving body, and a metal layer provided inward of the solar cell when viewed from the moving body. The metal layer is insulated from the solar cell and is electrically connected to ground potential.
    Type: Application
    Filed: March 23, 2015
    Publication date: July 9, 2015
    Inventors: Kenichi MAKI, Tetsuya KANEKO
  • Publication number: 20140158200
    Abstract: Provided is a solar module with improved reliability. A solar module (1) is provided with a solar cell (10), a wiring member (11), a resin adhesive layer (12), and a buffer region (40). The wiring member (11) is electrically connected to the solar cell (10). The resin adhesive layer (12) bonds the solar cell (10) and the wiring member (11) to one another. The buffer region (40) is provided at least partially between the wiring member (11) and the solar cell (10). The buffer region (40) contains a non-crosslinked resin.
    Type: Application
    Filed: February 18, 2014
    Publication date: June 12, 2014
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Kenichi Maki, Haruhisa Hashimoto
  • Patent number: 7948031
    Abstract: A semiconductor device includes a gate electrode formed through an insulating film in a groove having a first side surface adjacent to a source region and a base region, and a second conductive type first impurity region formed adjacent to a second side surface of the groove between the groove and a lead-out portion of a drain region existing below the base region so as to extend downward beyond a lower end of the groove.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: May 24, 2011
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Seiji Otake, Yasuhiro Takeda, Kenichi Maki
  • Patent number: 7768067
    Abstract: This invention provides a DMOS transistor that has a reduced ON resistance and is prevented from deterioration in strength against an electrostatic discharge. An edge portion of a source layer of the DMOS transistor is disposed so as to recede from an inner corner portion of a gate electrode. A silicide layer is structured so as not to extend out of the edge portion of the source layer. That is, although the silicide layer is formed on a surface of the source layer, the silicide layer is not formed on a surface of a portion of a body layer, which is exposed between the source layer and the inner corner portion of the gate electrode. As a result, the strength against the electrostatic discharge can be improved, because an electric current flows almost uniformly through whole of the DMOS transistor without converging.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: August 3, 2010
    Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Seiji Otake, Shuichi Kikuchi, Yasuhiro Takeda, Kenichi Maki
  • Publication number: 20090261410
    Abstract: This invention provides a DMOS transistor that has a reduced ON resistance and is prevented from deterioration in strength against an electrostatic discharge. An edge portion of a source layer of the DMOS transistor is disposed so as to recede from an inner corner portion of a gate electrode. A silicide layer is structured so as not to extend out of the edge portion of the source layer. That is, although the silicide layer is formed on a surface of the source layer, the silicide layer is not formed on a surface of a portion of a body layer, which is exposed between the source layer and the inner corner portion of the gate electrode. As a result, the strength against the electrostatic discharge can be improved, because an electric current flows almost uniformly through whole of the DMOS transistor without converging.
    Type: Application
    Filed: April 17, 2009
    Publication date: October 22, 2009
    Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventors: Seiji OTAKE, Shuichi Kikuchi, Yasuhiro Takeda, Kenichi Maki
  • Publication number: 20090014790
    Abstract: A semiconductor device includes a gate electrode formed through an insulating film in a groove having a first side surface adjacent to a source region and a base region, and a second conductive type first impurity region formed adjacent to a second side surface of the groove between the groove and a lead-out portion of a drain region existing below the base region so as to extend downward beyond a lower end of the groove.
    Type: Application
    Filed: July 3, 2008
    Publication date: January 15, 2009
    Applicants: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.
    Inventors: Seiji OTAKE, Yasuhiro TAKEDA, Kenichi MAKI
  • Patent number: 6199002
    Abstract: A control method and apparatus which detects a solenoid current as a voltage, and PWM-controls a transistor for a solenoid such that the detection voltage becomes a target voltage. A feedback gain, used for setting PWM signal output time, is set in accordance with the difference between the detection voltage and the target voltage such that the greater the difference becomes, the greater the feedback gain becomes. Further, a detection voltage after a predetermined period is estimated based on the change of detection voltage from the past. If the estimation value overshoots the target voltage, a difference B between the detection voltage and the target voltage and a difference C between the detection voltage and the estimation value are obtained, and the feedback gain is varied by multiplying the feedback gain by the ratio B/C between the these differences.
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: March 6, 2001
    Assignee: Denso Corporation
    Inventors: Tetsuya Otaki, Kenichi Maki, Masaya Oi, Koji Nagata
  • Patent number: 5572977
    Abstract: A fuel injection control system having an intelligent timer (TPU) to perform fuel injection control using the TPU even on request of asynchronous injection which is not synchronous with rotational angle signals. A central processing unit (CPU) calculates a value to be used during the execution of a synchronous injection (e.g., a fuel injection time) and an asynchronous injection time and stores these values in a parameter RAM. The CPU determines whether there is a request for an asynchronous injection from, for example, the quantity of a change in the opening of a throttle. The TPU also executes a synchronous injection if there is no asynchronous injection request. If there is an asynchronous injection request, it transmits an on output from input/output pins and causes a compare register to store a value which is the sum of the current time and an asynchronous injection time. It transmits an off output from the input/output pins if this value agrees with a value in a first free run counter.
    Type: Grant
    Filed: August 22, 1994
    Date of Patent: November 12, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hiroshi Shibata, Yoichi Nishiyori, Kenichi Maki, Hiroshi Kondo