Patents by Inventor Kenichi Nakanishi

Kenichi Nakanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210295914
    Abstract: A selector malfunction caused by a drift is prevented in a memory having a cross-point structure. A memory cell array is provided with a data area and a drift reference cell. An accumulated drift amount acquisition unit acquires an accumulated drift amount of the drift reference cell. A total drift amount reading unit reads a total drift amount stored in the data area. A refresh control unit adds the accumulated drift amount to the total drift amount to update the total drift amount as a new total drift amount. Further, the refresh control unit refreshes the data area of the memory cell array in a case where the new total drift amount exceeds a predetermined threshold value.
    Type: Application
    Filed: April 18, 2019
    Publication date: September 23, 2021
    Inventors: KEN ISHII, KENICHI NAKANISHI, HIDEAKI OKUBO, YOSHIYUKI SHIBAHARA, HARUHIKO TERADA
  • Publication number: 20210292462
    Abstract: A polyisocyanurate raw material composition containing a polyfunctional isocyanate, a compound (I) represented by general formula (I) shown below, and an epoxy compound. In general formula (I), each of R1 to R5 represents a hydrogen atom, an alkoxy group of 1 to 10 carbon atoms, an alkyl group of 2 to 10 carbon atoms (or an alkyl group of 1 to 10 carbon atoms in the case of R3 to R5), an aryl group of 6 to 12 carbon atoms, an amino group, a monoalkylamino group of 1 to 10 carbon atoms, a dialkylamino group of 2 to 20 carbon atoms, a carboxy group, a cyano group, a fluoroalkyl group of 1 to 10 carbon atoms, or a halogen atom (provide that R1 and R2 are not both hydrogen atoms).
    Type: Application
    Filed: July 11, 2019
    Publication date: September 23, 2021
    Applicant: SHOWA DENKO K.K.
    Inventors: Hiroki KURAMOTO, Kenichi NAKANISHI, Shohei NISHIZAWA, Yoshishige OKUNO
  • Publication number: 20210284800
    Abstract: Provided is a maleimide resin with superior solution stability. Also provided is a cured product with a superior dielectric characteristic that is obtained by curing a curable resin composition in which said maleimide resin is used. The maleimide resin expressed in formula (1). (In formula (1), each of the plurality of Rs independently represents a C1-5 alkyl group, n is the number of repetitions, and the average value thereof is 1<n<5.
    Type: Application
    Filed: September 4, 2019
    Publication date: September 16, 2021
    Applicant: NIPPONKAYAKU KABUSHIKI KAISHA
    Inventors: Kenichi KUBOKI, Masataka NAKANISHI, Kazuki MATSUURA
  • Patent number: 11117539
    Abstract: A seat device for a vehicle includes a seat for supporting a lower body of a vehicle occupant, and a backrest for supporting an upper body of the occupant. The seat device further includes an arresting portion that is stored in a storage position disposed in the seat. The arresting portion is configured to be deployed from the storage position and restrain a part of the lower body of the occupant from moving forward in the event of a collision of the vehicle.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: September 14, 2021
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Yasushi Masuda, Shigeyuki Suzuki, Shigemi Mase, Hiroaki Yamada, Tadashi Yamada, Yuji Sato, Kenichi Fukurono, Keisaku Yokoi, Takafumi Nakanishi, Takenori Ozaki
  • Publication number: 20210261736
    Abstract: Provided is a maleimide resin with superior solution stability. Also provided is a cured product with a superior dielectric characteristic that is obtained by curing a curable resin composition in which said maleimide resin is used. The maleimide resin expressed in formula (1), wherein the N,N?-(phenylene-di-(2,2,-propylidene)-di-p-phenylene) bismaleimide content is 90 area % or less. (In formula (1), n is the number of repetitions, and 1<n<5.
    Type: Application
    Filed: September 6, 2019
    Publication date: August 26, 2021
    Applicant: NIPPONKAYAKU KABUSHIKI KAISHA
    Inventors: Kenichi KUBOKI, Masataka NAKANISHI, Kazuki MATSUURA
  • Publication number: 20210257024
    Abstract: To eliminate drift that is generated in a memory cell and continue use of the memory cell. A storage control device controls a memory cell array in which each bit is in any one of first or second states. The storage control device includes a detection unit and a control unit. The detection unit detects a transition bit that should be in the first state but is in the second state in the memory cell array. The control unit performs control to supply, to the transition bit, a drift refresh voltage higher than a read voltage required for reading from the memory cell array.
    Type: Application
    Filed: March 5, 2019
    Publication date: August 19, 2021
    Inventors: HIDEAKI OKUBO, KENICHI NAKANISHI
  • Publication number: 20210256540
    Abstract: An integrated management server comprising: a data formatting means for receiving sales record information from a plurality of distributor terminals of a plurality of distributors which are selling products to retailers; a data matching means for updating brand master information for universally managing alcoholic beverage brands sold to the retailers across the plurality of distributors based on each of the received sales record information; and a brand Identification means for analyzing image related information received from a user terminal, identifying an alcoholic beverage brand by comparing a feature information corresponding to an alcoholic beverage brand registered in the brand master information, and sending information related to identified alcoholic beverage brand to the user terminal; and the user terminal comprising: a display means for displaying information on the sent alcoholic beverage brand.
    Type: Application
    Filed: January 28, 2021
    Publication date: August 19, 2021
    Inventor: Kenichi NAKANISHI
  • Patent number: 11029881
    Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 8, 2021
    Assignee: SONY CORPORATION
    Inventors: Ken Ishii, Hiroyuki Iwaki, Kenichi Nakanishi, Yasushi Fujinami, Tatsuo Shinbashi
  • Patent number: 11023381
    Abstract: An object is to suppress a process of evicting cached data so as to improve a throughput of an entire system. A storage controller includes an access request section and an operation management section. The access request section requests access to a first storage and to a second storage that is higher in response speed than the first storage, the second storage storing part of data stored in the first storage. The operation management section manages, based on a usage state of the second storage, whether or not to transfer from the first storage to the second storage data targeted for access but not stored in the second storage.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: June 1, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Teruya Kaneda, Kenichi Nakanishi, Hideaki Okubo
  • Patent number: 11016703
    Abstract: A delay due to retry processing with regard to occurrence of a memory write error is suppressed. A sub-region command holding section holds a host command as a sub-region command divided with respect to each access target sub-region. A sub-region address conversion section converts an address of an access target sub-region to an address of a memory regarding a sub-region command. A sub-region command execution section executes a sub-region command whose address has been converted, and accesses a memory. In a case where a write error occurs in a memory regarding a sub-region command, an address conversion management section performs preparation processing of a substitute region for a sub-region command in which the write error has occurred concurrently with execution of another sub-region command in the sub-region command execution section.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: May 25, 2021
    Assignee: SONY CORPORATION
    Inventor: Kenichi Nakanishi
  • Publication number: 20210081136
    Abstract: Efficient wear leveling processing is performed in a memory in which the number of times of writing may vary for each of pages that are access units. An address conversion unit performs address conversion between a logical address of a host command and a physical address of the memory for each of management units, the management units each including a plurality of access units of the memory. A write amount measurement unit measures a write amount for each of the access units in each of the management units. The averaging processing unit selects a target management unit from the management units on the basis of the write amount measured by the write amount measurement unit and changes physical address allocation in the address conversion of the target management unit. Then, the averaging processing unit performs processing of averaging write amounts of the access units in the target management unit.
    Type: Application
    Filed: April 3, 2018
    Publication date: March 18, 2021
    Inventor: KENICHI NAKANISHI
  • Publication number: 20200364109
    Abstract: A load of a data channel at the time of data writing is reduced. A memory controller includes a specific data pattern retaining unit, a comparator, and an issuance unit. The specific data pattern retaining unit retains a specific data pattern. The comparator compares write data regarding a write command from a host computer with the specific data pattern. The issuance unit issues a specific write request that requests writing of the specific data pattern without supplying the write data to a memory in a case where the write data matches the specific data pattern.
    Type: Application
    Filed: August 6, 2018
    Publication date: November 19, 2020
    Inventors: HIROYUKI IWAKI, KENICHI NAKANISHI
  • Publication number: 20200310681
    Abstract: The order of read access to a memory is appropriately determined. A memory system includes a plurality of memories and a memory controller. The memory controller includes a memory write control unit and a memory read control unit. The memory write control unit generates a write request for any one of the plurality of memories on the basis of a write command from a computer. The memory read control unit generates a read request for any one of the plurality of memories according to priority corresponding to a data processing state of write data related to the write request in the memory write control unit on the basis of a read command from the computer.
    Type: Application
    Filed: April 17, 2017
    Publication date: October 1, 2020
    Inventors: KEN ISHII, HIROYUKI IWAKI, KENICHI NAKANISHI, YASUSHI FUJINAMI, TATSUO SHINBASHI
  • Publication number: 20200301843
    Abstract: Memory devices having different parallel accessible data sizes and different access speeds are caused to work efficiently as a cache memory. A memory access device accesses first and second memory devices that respectively include a plurality of parallel accessible memories and have different parallel accessible data sizes and different access speeds. The memory access device includes a management information storage unit and an access control unit. The management information storage unit stores management information as associating each corresponding management unit of the first and second memory devices. The access control unit accesses one of the first and second memory devices on the basis of the management information.
    Type: Application
    Filed: July 5, 2018
    Publication date: September 24, 2020
    Inventors: HIDEAKI OKUBO, KENICHI NAKANISHI, TERUYA KANEDA
  • Publication number: 20200117601
    Abstract: An object is to suppress a process of evicting cached data so as to improve a throughput of an entire system. A storage controller includes an access request section and an operation management section. The access request section requests access to a first storage and to a second storage that is higher in response speed than the first storage, the second storage storing part of data stored in the first storage. The operation management section manages, based on a usage state of the second storage, whether or not to transfer from the first storage to the second storage data targeted for access but not stored in the second storage.
    Type: Application
    Filed: February 5, 2018
    Publication date: April 16, 2020
    Inventors: TERUYA KANEDA, KENICHI NAKANISHI, HIDEAKI OKUBO
  • Patent number: 10545804
    Abstract: [Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: January 28, 2020
    Assignee: Sony Corporation
    Inventors: Tatsuo Shinbashi, Keiichi Tsutsui, Hideaki Okubo, Lui Sakai, Kenichi Nakanishi, Yasushi Fujinami
  • Patent number: 10540275
    Abstract: To secure flexibility of the memory extension area which is secured on the memory of the host computer and used by the memory controller. [Solution] A controller memory stores data corresponding to an area allocated to a memory in a memory controller configured to control the memory. An access control unit allocates a partial area of the controller memory to a host memory in a host computer and uses the areas as a memory extension area. The extension area managing unit performs management so that a size of the memory extension area in the host memory is changeable.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: January 21, 2020
    Assignee: Sony Corporation
    Inventors: Hideaki Okubo, Kenichi Nakanishi, Yasushi Fujinami
  • Patent number: 10528287
    Abstract: To enhance accuracy of counting the number of rewrite cycles in a non-volatile memory that is overwritable. A memory outputs erase information that is information regarding whether or not erase processing has been performed in writing of data in units of pages each including a plurality of memory cells in which data is rewritten by program processing of shifting a memory cell that stores data from an initial state to a data-storing state and erase processing of shifting the memory cell from the data-storing state to the initial state. The number of rewrite cycles is counted by updating the number of rewrite cycles on a basis of the output erase information.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: January 7, 2020
    Assignee: SONY CORPORATION
    Inventor: Kenichi Nakanishi
  • Patent number: 10481971
    Abstract: A data holding characteristic of a memory cell is improved in a memory system in which data is encoded and written to a memory cell. A first candidate parity generation unit generates, as a first candidate parity, a parity for detecting an error in an information section in which a predetermined value is assigned in a predetermined variable area. A second candidate parity generation unit generates, as a second candidate parity, a parity for detecting an error in the information section in which a value different from the predetermined value is assigned in the predetermined variable area. A selection unit selects a parity that satisfies a predetermined condition from among the first and second candidate parities as a selection parity. An output unit outputs a codeword constituted by the information section corresponding to the selection parity and the selection parity.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: November 19, 2019
    Assignee: Sony Corporation
    Inventors: Tatsuo Shinbashi, Kenichi Nakanishi, Yasushi Fujinami, Hiroyuki Iwaki, Ken Ishii, Hideaki Okubo
  • Publication number: 20190205065
    Abstract: A delay due to retry processing with regard to occurrence of a memory write error is suppressed. A sub-region command holding section holds a host command as a sub-region command divided with respect to each access target sub-region. A sub-region address conversion section converts an address of an access target sub-region to an address of a memory regarding a sub-region command. A sub-region command execution section executes a sub-region command whose address has been converted, and accesses a memory. In a case where a write error occurs in a memory regarding a sub-region command, an address conversion management section performs preparation processing of a substitute region for a sub-region command in which the write error has occurred concurrently with execution of another sub-region command in the sub-region command execution section.
    Type: Application
    Filed: July 27, 2017
    Publication date: July 4, 2019
    Inventor: KENICHI NAKANISHI