Patents by Inventor Kenichi Shimamoto

Kenichi Shimamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190148172
    Abstract: A semiconductor chip has a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies the second signal and outputs a third signal, and a semiconductor substrate having a main surface parallel to a plane defined by first and second directions and which has the first and second transistors formed thereon. The main surface has thereon a first bump connected to a collector or drain of the first transistor, a second bump connected to an emitter or source of the first transistor, a third bump connected to a collector or drain of the second transistor, and a fourth bump connected to an emitter or source of the second transistor. The first bump is circular, the second through fourth bumps are rectangular or oval, and the area of each of the second through fourth bumps is larger than that of the first bump.
    Type: Application
    Filed: January 8, 2019
    Publication date: May 16, 2019
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Kenichi SHIMAMOTO
  • Publication number: 20190140596
    Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 9, 2019
    Inventors: Kenichi SHIMAMOTO, Satoshi TANAKA, Tadashi MATSUOKA
  • Patent number: 10270400
    Abstract: A semiconductor device includes a semiconductor substrate having a principal surface which has a first side in a first direction and a second side in a second direction. A plurality of transistor arrays is formed in a region adjacent to the first side of the semiconductor substrate. A plurality of bumps include first and second bumps which are longer in the first direction. The distance between the first side and the first bump is shorter than the distance between the first side and the second bump. The plurality of transistor arrays include a first and a second transistor arrays. The first transistor array has a plurality of first unit transistors arranged along the first direction such that the first unit transistors overlap the first bump. The second transistor array has a plurality of second unit transistors arranged along the first direction such that the second unit transistors overlap the second bump.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: April 23, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Kenichi Shimamoto
  • Patent number: 10236828
    Abstract: A power amplifier has improved power added efficiency at high output power. The power amplifier includes: a first transistor for amplifying an input signal input to the base thereof and outputting the amplified signal from the collector thereof; a second transistor with power-supply voltage applied to the collector thereof to supply bias voltage or bias current from the emitter thereof to the base of the first transistor; a third transistor whose collector is connected to the collector of the first transistor to amplify the input signal input to the base thereof and output the amplified signal from a collector thereof; a fourth transistor whose base and collector are connected to supply bias from the emitter thereof to the base of the third transistor; and a first resistor with bias control voltage applied to one end thereof and the other end connected to the bases of the second and fourth transistors.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 19, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuma Sugiura, Takashi Yamada, Norio Hayashi, Satoshi Tanaka, Kenichi Shimamoto, Kazuo Watanabe
  • Patent number: 10211783
    Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: February 19, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kenichi Shimamoto, Satoshi Tanaka, Tadashi Matsuoka
  • Patent number: 10211073
    Abstract: A semiconductor chip has a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies the second signal and outputs a third signal, and a semiconductor substrate having a main surface parallel to a plane defined by first and second directions and which has the first and second transistors formed thereon. The main surface has thereon a first bump connected to a collector or drain of the first transistor, a second bump connected to an emitter or source of the first transistor, a third bump connected to a collector or drain of the second transistor, and a fourth bump connected to an emitter or source of the second transistor. The first bump is circular, the second through fourth bumps are rectangular or oval, and the area of each of the second through fourth bumps is larger than that of the first bump.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: February 19, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kenichi Shimamoto
  • Publication number: 20180309412
    Abstract: A power amplification circuit includes: a first amplification transistor, a first signal being input to a base or gate thereof and a second signal obtained by amplifying the first signal being output from a collector or drain thereof; and a first bias circuit that supplies a first bias current to the base or gate of the first amplification transistor. The first bias circuit includes a first transistor that outputs the first bias current from an emitter or source thereof, and a first control circuit that controls an electrical connection between the emitter or source of the first transistor and ground. The first control circuit includes a first resistance element and a first switch element, which are connected in series with each other. The first switch element is switched on in the case of a first power mode and is switched off in the case of a second power mode.
    Type: Application
    Filed: June 28, 2018
    Publication date: October 25, 2018
    Inventor: Kenichi SHIMAMOTO
  • Publication number: 20180262167
    Abstract: A semiconductor device includes a semiconductor substrate having a principal surface which has a first side in a first direction and a second side in a second direction. A plurality of transistor arrays is formed in a region adjacent to the first side of the semiconductor substrate. A plurality of bumps include first and second bumps which are longer in the first direction. The distance between the first side and the first bump is shorter than the distance between the first side and the second bump. The plurality of transistor arrays include a first and a second transistor arrays. The first transistor array has a plurality of first unit transistors arranged along the first direction such that the first unit transistors overlap the first bump. The second transistor array has a plurality of second unit transistors arranged along the first direction such that the second unit transistors overlap the second bump.
    Type: Application
    Filed: May 10, 2018
    Publication date: September 13, 2018
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kenji SASAKI, Kenichi SHIMAMOTO
  • Publication number: 20180218921
    Abstract: A semiconductor chip has a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies the second signal and outputs a third signal, and a semiconductor substrate having a main surface parallel to a plane defined by first and second directions and which has the first and second transistors formed thereon. The main surface has thereon a first bump connected to a collector or drain of the first transistor, a second bump connected to an emitter or source of the first transistor, a third bump connected to a collector or drain of the second transistor, and a fourth bump connected to an emitter or source of the second transistor. The first bump is circular, the second through fourth bumps are rectangular or oval, and the area of each of the second through fourth bumps is larger than that of the first bump.
    Type: Application
    Filed: December 20, 2017
    Publication date: August 2, 2018
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Kenichi SHIMAMOTO
  • Patent number: 10038410
    Abstract: A power amplification circuit includes: a first amplification transistor, a first signal being input to a base or gate thereof and a second signal obtained by amplifying the first signal being output from a collector or drain thereof; and a first bias circuit that supplies a first bias current to the base or gate of the first amplification transistor. The first bias circuit includes a first transistor that outputs the first bias current from an emitter or source thereof, and a first control circuit that controls an electrical connection between the emitter or source of the first transistor and ground. The first control circuit includes a first resistance element and a first switch element, which are connected in series with each other. The first switch element is switched on in the case of a first power mode and is switched off in the case of a second power mode.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: July 31, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kenichi Shimamoto
  • Patent number: 10003307
    Abstract: A semiconductor device includes a semiconductor substrate having a principal surface which has a first side in a first direction and a second side in a second direction. A plurality of transistor arrays is formed in a region adjacent to the first side of the semiconductor substrate. A plurality of bumps include first and second bumps which are longer in the first direction. The distance between the first side and the first bump is shorter than the distance between the first side and the second bump. The plurality of transistor arrays include a first and a second transistor arrays. The first transistor array has a plurality of first unit transistors arranged along the first direction such that the first unit transistors overlap the first bump. The second transistor array has a plurality of second unit transistors arranged along the first direction such that the second unit transistors overlap the second bump.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: June 19, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Kenichi Shimamoto
  • Publication number: 20180062586
    Abstract: A semiconductor device includes a semiconductor substrate having a principal surface which has a first side in a first direction and a second side in a second direction. A plurality of transistor arrays is formed in a region adjacent to the first side of the semiconductor substrate. A plurality of bumps include first and second bumps which are longer in the first direction. The distance between the first side and the first bump is shorter than the distance between the first side and the second bump. The plurality of transistor arrays include a first and a second transistor arrays. The first transistor array has a plurality of first unit transistors arranged along the first direction such that the first unit transistors overlap the first bump. The second transistor array has a plurality of second unit transistors arranged along the first direction such that the second unit transistors overlap the second bump.
    Type: Application
    Filed: August 10, 2017
    Publication date: March 1, 2018
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Kenji SASAKI, Kenichi SHIMAMOTO
  • Publication number: 20180041169
    Abstract: A power amplifier has improved power added efficiency at high output power. The power amplifier includes: a first transistor for amplifying an input signal input to the base thereof and outputting the amplified signal from the collector thereof; a second transistor with power-supply voltage applied to the collector thereof to supply bias voltage or bias current from the emitter thereof to the base of the first transistor; a third transistor whose collector is connected to the collector of the first transistor to amplify the input signal input to the base thereof and output the amplified signal from a collector thereof; a fourth transistor whose base and collector are connected to supply bias from the emitter thereof to the base of the third transistor; and a first resistor with bias control voltage applied to one end thereof and the other end connected to the bases of the second and fourth transistors.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 8, 2018
    Inventors: Kazuma Sugiura, Takashi Yamada, Norio Hayashi, Satoshi Tanaka, Kenichi Shimamoto, Kazuo Watanabe
  • Publication number: 20170317650
    Abstract: A power amplification circuit includes: a first amplification transistor, a first signal being input to a base or gate thereof and a second signal obtained by amplifying the first signal being output from a collector or drain thereof; and a first bias circuit that supplies a first bias current to the base or gate of the first amplification transistor. The first bias circuit includes a first transistor that outputs the first bias current from an emitter or source thereof, and a first control circuit that controls an electrical connection between the emitter or source of the first transistor and ground. The first control circuit includes a first resistance element and a first switch element, which are connected in series with each other. The first switch element is switched on in the case of a first power mode and is switched off in the case of a second power mode.
    Type: Application
    Filed: July 14, 2017
    Publication date: November 2, 2017
    Inventor: Kenichi SHIMAMOTO
  • Publication number: 20170288611
    Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 5, 2017
    Inventors: Kenichi Shimamoto, Satoshi Tanaka, Tadashi Matsuoka
  • Patent number: 9768729
    Abstract: A power amplifier has improved power added efficiency at high output power. The power amplifier includes: a first transistor for amplifying an input signal input to the base thereof and outputting the amplified signal from the collector thereof; a second transistor with power-supply voltage applied to the collector thereof to supply bias voltage or bias current from the emitter thereof to the base of the first transistor; a third transistor whose collector is connected to the collector of the first transistor to amplify the input signal input to the base thereof and output the amplified signal from a collector thereof; a fourth transistor whose base and collector are connected to supply bias from the emitter thereof to the base of the third transistor; and a first resistor with bias control voltage applied to one end thereof and the other end connected to the bases of the second and fourth transistors.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: September 19, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kazuma Sugiura, Takashi Yamada, Norio Hayashi, Satoshi Tanaka, Kenichi Shimamoto, Kazuo Watanabe
  • Patent number: 9742358
    Abstract: A power amplification circuit includes: a first amplification transistor, a first signal being input to a base or gate thereof and a second signal obtained by amplifying the first signal being output from a collector or drain thereof; and a first bias circuit that supplies a first bias current to the base or gate of the first amplification transistor. The first bias circuit includes a first transistor that outputs the first bias current from an emitter or source thereof, and a first control circuit that controls an electrical connection between the emitter or source of the first transistor and ground. The first control circuit includes a first resistance element and a first switch element, which are connected in series with each other. The first switch element is switched on in the case of a first power mode and is switched off in the case of a second power mode.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: August 22, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kenichi Shimamoto
  • Patent number: 9722542
    Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: August 1, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kenichi Shimamoto, Satoshi Tanaka, Tadashi Matsuoka
  • Publication number: 20170163223
    Abstract: A power amplification circuit includes: a first amplification transistor, a first signal being input to a base or gate thereof and a second signal obtained by amplifying the first signal being output from a collector or drain thereof; and a first bias circuit that supplies a first bias current to the base or gate of the first amplification transistor. The first bias circuit includes a first transistor that outputs the first bias current from an emitter or source thereof, and a first control circuit that controls an electrical connection between the emitter or source of the first transistor and ground. The first control circuit includes a first resistance element and a first switch element, which are connected in series with each other. The first switch element is switched on in the case of a first power mode and is switched off in the case of a second power mode.
    Type: Application
    Filed: November 30, 2016
    Publication date: June 8, 2017
    Inventor: Kenichi SHIMAMOTO
  • Publication number: 20160285423
    Abstract: A power amplification module includes a first transistor which amplifies and outputs a radio frequency signal input to its base; a current source which outputs a control current; a second transistor connected to an output of the current source, a first current from the control current input to its collector, a control voltage generation circuit connected to the output and which generates a control voltage according to a second current from the control current; a first FET, the drain being supplied with a supply voltage, the source being connected to the base of the first transistor, and the gate being supplied with the control voltage; and a second FET, the drain being supplied with the supply voltage, the source being connected to the base of the second transistor, and the gate being supplied with the control voltage.
    Type: Application
    Filed: June 10, 2016
    Publication date: September 29, 2016
    Inventors: Kenichi Shimamoto, Satoshi Tanaka, Tadashi Matsuoka