Patents by Inventor Kenichi Shimomura

Kenichi Shimomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230290791
    Abstract: There are provided an imaging device and an electronic device that minimize an ineffective region inside a pixel and achieve reduction in size, high SN, high sensitivity, high resolution, and a reduced afterimage.
    Type: Application
    Filed: August 5, 2021
    Publication date: September 14, 2023
    Inventors: Takumi YAMAGUCHI, Kenichi SHIMOMURA, Shiro DEGUCHI
  • Publication number: 20230064713
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory opening fill structures vertically extending through the alternating stack. An insulating liner overlies stepped surfaces of the alternating stack in a staircase region. A plurality of discrete dielectric plates can be formed over the insulating liner. In one embodiment, the plurality of discrete dielectric plates can function as etch stop structures for formation of contact via structures that contact underlying portions of the electrically conductive layers. In another embodiment, the plurality of discrete dielectric plates may be replaced with a metallic material that forms extensions of the electrically conductive layers, and can be employed as etch stop structures during formation of contact via structures.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 2, 2023
    Inventor: Kenichi SHIMOMURA
  • Publication number: 20230069307
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory opening fill structures vertically extending through the alternating stack. An insulating liner overlies stepped surfaces of the alternating stack in a staircase region. A plurality of discrete dielectric plates can be formed over the insulating liner. In one embodiment, the plurality of discrete dielectric plates can function as etch stop structures for formation of contact via structures that contact underlying portions of the electrically conductive layers. In another embodiment, the plurality of discrete dielectric plates may be replaced with a metallic material that forms extensions of the electrically conductive layers, and can be employed as etch stop structures during formation of contact via structures.
    Type: Application
    Filed: August 25, 2021
    Publication date: March 2, 2023
    Inventor: Kenichi SHIMOMURA
  • Publication number: 20220352196
    Abstract: Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least one additional dielectric spacer.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 3, 2022
    Inventors: Kenichi SHIMOMURA, Koichi MATSUNO, Johann ALSMEIER
  • Publication number: 20220302146
    Abstract: A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers, a second-tier alternating stack of second insulating layers and second electrically conductive layers, a vertically alternating sequence of insulating plates and dielectric material plates laterally surrounded by the second-tier alternating stack, memory openings vertically extending through each layer within the first-tier alternating stack and the second-tier alternating stack, memory opening fill structures located in the memory openings, first contact via structures vertically extending through the vertically alternating sequence and contacting a respective one of the first electrically conductive layers, and second contact via structures contacting a respective one of the second electrically conductive layers.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 22, 2022
    Inventors: Kenichi SHIMOMURA, Takayuki MAEKURA
  • Patent number: 9019142
    Abstract: In a solid-state imaging device which includes column analog-to-digital conversion circuits (ADCs) for converting pixel signals output from pixels into digital signals, each of the column ADCs includes a comparator which outputs a result of voltage comparison (comparison result signal) between the voltage of the pixel signal and an analog ramp voltage; a column counter which counts a column counter clock signal, which is either a clock signal or a phase-shifted clock signal, and stores a value represented by upper bits of a count value at a time of change in the comparison result signal; and a first latch unit which stores a value represented by lower bits of the count value. A second latch unit stores the value stored in the first latch unit.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: April 28, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Toshiaki Hiraoka, Kenichi Shimomura, Yutaka Abe, Yusuke Shimizu
  • Patent number: 8735796
    Abstract: A solid-state imaging device includes: a column comparison circuit which compares a pixel signal with ramp waves and detects a timing at which the pixel signal and the ramp waves match; a counter circuit which is disposed for each of the pixel columns and measures the timing in the column comparison circuit by being supplied with a clock signal; and M first inverters which are equidistantly connected in series, wherein the counter circuit belongs to one of M groups corresponding to each of the M first inverters disposed in the upper clock stage, the odd-numbered group has second inverters disposed between the output terminal of the first inverter corresponding to the group and the counter circuit of the group, and the even-numbered group has buffers disposed between the output terminal of the first inverter corresponding to the group and the counter circuit of the group.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: May 27, 2014
    Assignee: Panasonic Corporation
    Inventors: Yusuke Shimizu, Kenichi Shimomura
  • Publication number: 20140036119
    Abstract: The solid-state imaging device according to the present invention includes a valid pixel area, a horizontal OB area, and a peripheral circuit area. The valid pixel area includes valid pixel cells from each of which an image signal corresponding to incident light is outputted. The horizontal OB area includes light-blocking pixel cells from each of which a black level signal not depending on the incident light. The peripheral circuit area includes a peripheral circuit. When (i) the valid pixel area has N line layers, (ii) each of the horizontal OB area and the peripheral circuit area has M line layers, and (iii) N<M, an (N+2)th line layer blocks light incident on the horizontal OB area, and an interlayer insulating film is filled between the (N+2)th line layer and the N-th line layer in the horizontal OB area.
    Type: Application
    Filed: October 9, 2013
    Publication date: February 6, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Kenichi SHIMOMURA, Hiroshi FUJINAKA, Hirohisa OHTSUKI
  • Patent number: 8502889
    Abstract: A solid-state image capturing device includes: a pixel array including a plurality of two-dimensionally arrayed pixels; a row scanning circuit that performs row scanning to sequentially select a row; a column ADC circuit that simultaneously converts analog pixel signals output from the plurality of pixels belonging to a row selected by the row scanning circuit into pieces of digital pixel data; a column digital memory that stores pixel data of one row therein; and a one-line compression circuit that sequentially performs compression coding to pixel data output from the column digital memory. In the solid-state image capturing device, when performing the compression coding to the pixel data, the one-line compression circuit refers to pixel data belonging to a row identical to that of the pixel data in question while not referring to pixel data belonging to a row different from that of the pixel data in question.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: August 6, 2013
    Assignee: Panasonic Corporation
    Inventors: Toshiaki Hiraoka, Kenichi Shimomura
  • Patent number: 8476568
    Abstract: A solid-state imaging device comprises a pixel array; a reference signal generation unit operable to generate a reference signal that changes monotonically for a predetermined period in a horizontal period; a comparator operable to compare the level of a pixel signal with the level of a reference signal; a counter operable to count input clock pulses; a memory operable to store the number of counts counted by the counter as a digital value; and a timing control unit operable to generate a clock that is to be input into the counter, and change frequency of the clock that is to be input into the counter based on external input data.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: July 2, 2013
    Assignee: Panasonic Corporation
    Inventors: Masashi Murakami, Kenichi Shimomura
  • Patent number: 8395688
    Abstract: The solid-state imaging device according to the present invention includes: pixel units arranged two-dimensionally in rows and columns; signal holding units each holding an analog signal outputted from one of the pixel units in a corresponding one of the columns; and column AD circuits each converting, into a digital signal, the analog signal held by a corresponding one of said signal holding units. The signal holding units and the column AD circuits are respectively provided for the columns of the pixel units. Each of the signal holding units includes: a switching element connected to a column signal line through which the analog signal outputted from the one of the pixel units is transmitted; and a capacitor element holding the analog signal and being connected to the column signal line through the switching element.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: March 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Masashi Murakami, Kenji Watanabe, Masayuki Hirota, Kenichi Shimomura
  • Publication number: 20120305752
    Abstract: A solid-state imaging device includes: a column comparison circuit which compares a pixel signal with ramp waves and detects a timing at which the pixel signal and the ramp waves match; a counter circuit which is disposed for each of the pixel columns and measures the timing in the column comparison circuit by being supplied with a clock signal; and M first inverters which are equidistantly connected in series, wherein the counter circuit belongs to one of M groups corresponding to each of the M first inverters disposed in the upper clock stage, the odd-numbered group has second inverters disposed between the output terminal of the first inverter corresponding to the group and the counter circuit of the group, and the even-numbered group has buffers disposed between the output terminal of the first inverter corresponding to the group and the counter circuit of the group.
    Type: Application
    Filed: August 16, 2012
    Publication date: December 6, 2012
    Inventors: Yusuke SHIMIZU, Kenichi SHIMOMURA
  • Patent number: 8310581
    Abstract: A row scanner selects an arbitrary row in an pixel array unit. Per-column AD converters separately convert voltage signals respectively outputted from a column of a plurality of unit pixels in the selected arbitrary row into digital signals. A column scanner sequentially outputs the digital signals by a column-scanning operation thereof. An AD conversion result adjuster judges whether or not the digital signals reach a predetermined judgment value or the status equivalent to the digital signals reaching the predetermined judgment value is generated, and fixes the digital signals to digital pixel values set in accordance with the predetermined judgment value when a result of the judgment is positive.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: November 13, 2012
    Assignee: Panasonic Corporation
    Inventors: Keijirou Itakura, Kenichi Shimomura
  • Publication number: 20120147209
    Abstract: A solid-state image capturing device includes: a pixel array including a plurality of two-dimensionally arrayed pixels; a row scanning circuit that performs row scanning to sequentially select a row; a column ADC circuit that simultaneously converts analog pixel signals output from the plurality of pixels belonging to a row selected by the row scanning circuit into pieces of digital pixel data; a column digital memory that stores pixel data of one row therein; and a one-line compression circuit that sequentially performs compression coding to pixel data output from the column digital memory. In the solid-state image capturing device, when performing the compression coding to the pixel data, the one-line compression circuit refers to pixel data belonging to a row identical to that of the pixel data in question while not referring to pixel data belonging to a row different from that of the pixel data in question.
    Type: Application
    Filed: February 21, 2012
    Publication date: June 14, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: TOSHIAKI HIRAOKA, KENICHI SHIMOMURA
  • Patent number: 8198575
    Abstract: A solid-state imaging device comprises a pixel array; a reference signal generation unit operable to generate a reference signal that changes monotonically for a predetermined period in a horizontal period; a comparator operable to compare the level of a pixel signal with the level of a reference signal; a counter operable to count input clock pulses; a memory operable to store the number of counts counted by the counter as a digital value; and a timing control unit operable to generate a clock that is to be input into the counter, and change frequency of the clock that is to be input into the counter based on external input data.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: June 12, 2012
    Assignee: Panasonic Corporation
    Inventors: Masashi Murakami, Kenichi Shimomura
  • Patent number: 8039781
    Abstract: In a solid state imaging device to be included in an imaging device such as a digital camera, a ramp run-up AD conversion circuit for AD converting a pixel signal is provided corresponding to one or a plurality of pixel columns. A column counter provided in each ramp run-up AD conversion circuit holds an upper bit, and a clock signal is supplied to one or plural latches for holding a lower bit. Thus, fast and accurate AD conversion can be realized while suppressing increase of clock frequency.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: October 18, 2011
    Assignee: Panasonic Corporation
    Inventors: Kenichi Shimomura, Kenji Watanabe, Yutaka Abe
  • Publication number: 20110157442
    Abstract: A row scanner selects an arbitrary row in an pixel array unit. Per-column AD converters separately convert voltage signals respectively outputted from a column of a plurality of unit pixels in the selected arbitrary row into digital signals. A column scanner sequentially outputs the digital signals by a column-scanning operation thereof. An AD conversion result adjuster judges whether or not the digital signals reach a predetermined judgment value or the status equivalent to the digital signals reaching the predetermined judgment value is generated, and fixes the digital signals to digital pixel values set in accordance with the predetermined judgment value when a result of the judgment is positive.
    Type: Application
    Filed: March 8, 2011
    Publication date: June 30, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Keijirou Itakura, Kenichi Shimomura
  • Patent number: 7952510
    Abstract: It is an object of the present invention to provide a solid-state imaging device for enhancing accuracy of AD conversion and active switching of up-counting and down-counting in the asynchronous counter without limiting the AD conversion frequency. The solid-state imaging device according to the present invention includes an asynchronous counter having an up-counting mode in which up-counting is performed, a down-counting mode in which down-counting is performed, and a holding mode for switching operation settings between the up-counting and the down-counting while maintaining a count value held in the asynchronous counter.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: May 31, 2011
    Assignee: PANASONIC Corporation
    Inventors: Kenichi Shimomura, Kenji Watanabe
  • Patent number: 7924335
    Abstract: A row scanner selects an arbitrary row in an pixel array unit. Per-column AD converters separately convert voltage signals respectively outputted from a column of a plurality of unit pixels in the selected arbitrary row into digital signals. A column scanner sequentially outputs the digital signals by a column-scanning operation thereof. An AD conversion result adjuster judges whether or not the digital signals reach a predetermined judgment value or the status equivalent to the digital signals reaching the predetermined judgment value is generated, and fixes the digital signals to digital pixel values set in accordance with the predetermined judgment value when a result of the judgment is positive.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: April 12, 2011
    Assignee: Panasonic Corporation
    Inventors: Keijirou Itakura, Kenichi Shimomura
  • Publication number: 20100277632
    Abstract: A solid-state imaging device comprises a pixel array; a reference signal generation unit operable to generate a reference signal that changes monotonically for a predetermined period in a horizontal period; a comparator operable to compare the level of a pixel signal with the level of a reference signal; a counter operable to count input clock pulses; a memory operable to store the number of counts counted by the counter as a digital value; and a timing control unit operable to generate a clock that is to be input into the counter, and change frequency of the clock that is to be input into the counter based on external input data.
    Type: Application
    Filed: July 8, 2010
    Publication date: November 4, 2010
    Applicant: Panasonic Corporation
    Inventors: Masashi Murakami, Kenichi Shimomura