Patents by Inventor Kenichi Takeda

Kenichi Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140117811
    Abstract: A lead-free piezoelectric element that stably operates in a wide operating temperature range contains a lead-free piezoelectric material. The piezoelectric element includes a first electrode, a second electrode, and a piezoelectric material that includes a perovskite-type metal oxide represented by (Ba1-xCax)a(Ti1-yZry)O3 (1.00?a?1.01, 0.02?x?0.30, 0.020?y?0.095, and y?x) as a main component and manganese incorporated in the perovskite-type metal oxide. The manganese content relative to 100 parts by weight of the perovskite-type metal oxide is 0.02 parts by weight or more and 0.40 parts by weight or less on a metal basis.
    Type: Application
    Filed: June 26, 2012
    Publication date: May 1, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Jumpei Hayashi, Kenichi Takeda, Shinya Koyama, Kenichi Akashi, Tatsuo Furuta
  • Patent number: 8618667
    Abstract: A bump electrode, a dummy bump, and a heat-resistant polymer film, whose upper-surface heights are uniformed, are formed on each of a first silicon substrate and a second silicon substrate, and then, the first silicon substrate and the second silicon substrate are bonded to each other so that the bump electrodes formed on the respective substrates are electrically connected to each other. At this time, the dummy bump is arranged so as to be bonded to the heat-resistant polymer film on the silicon substrate opposed thereto, so that a semiconductor device having both of good electrical connection between the bump electrodes and bump protection performance obtained by a polymer film with high heat resistance and without voids can be achieved.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: December 31, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Kenichi Takeda, Mayu Aoki, Kazuyuki Hozawa
  • Publication number: 20130285253
    Abstract: A method of manufacturing a semiconductor device includes: a step of forming an inorganic insulating film and an organic insulating film on one surface of a first substrate; a step of forming an opening portion by dry-etching a laminated film of them; a step of forming a bump electrode inside the opening portion; and a step (bonding step) of bonding the one surface of the first substrate having a bump electrode formed thereon and one surface of a second substrate having a bump electrode formed thereon to each other. A surface treatment on the inorganic insulating film is performed subsequent to the step of forming the opening portion but prior to the bonding step. By performing the surface treatment on the organic insulating film, connecting property between the substrates can be improved.
    Type: Application
    Filed: March 15, 2013
    Publication date: October 31, 2013
    Applicant: HITACHI, LTD.
    Inventors: Mayu Aoki, Kenichi Takeda, Kazuyuki Hozawa
  • Patent number: 8480918
    Abstract: The present invention provides a piezoelectric material which can be applied even to the MEMS technique, exhibits satisfactory piezoelectricity even at high ambient temperatures and is environmentally clean, namely, a piezoelectric material including an oxide obtained by forming a solid solution composed of two perovskite oxides A(1)B(1)O3 and A(2)B(2)O3 different from each other in crystalline phase, the oxide being represented by the following general formula (1): X{A(1)B(1)O3}?(1?X){A(2)B(2)O3}??(1) wherein “A(1)” and “A(2)” are each an element including an alkali earth metal and may be the same or different from each other; “B(1)” and “B(2)” each include two or more metal elements, and either one of “B(1)” and “B(2)” contains Cu in a content of 3 atm % or more; and “X” satisfies the relation 0<X<1.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: July 9, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kaoru Miura, Toshihiro Ifuku, Kenichi Takeda, Tetsuro Fukui, Hiroshi Funakubo
  • Patent number: 8410615
    Abstract: A semiconductor device including two silicon wafers stacked and bonded together with bumps of one wafer electrically coupled with those of the other wafer, in which generation of voids on the junction surface between the silicon wafers is suppressed. Due to a recess made in the surface of a buried conductive film, a cavity is formed in the junction surface between the silicon wafers. The ends of the cavity extend to the periphery of the junction surface between the silicon wafers. This allows the air trapped on the junction surface between the silicon wafers to get out through the cavity, thereby reducing the possibility of generation of voids on the junction surface.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: April 2, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Mayu Aoki, Kenichi Takeda, Kazuyuki Hozawa
  • Publication number: 20120319533
    Abstract: Provided are a piezoelectric thin film having good piezoelectricity in which a rhombohedral structure and a tetragonal structure are mixed, and a piezoelectric element using the piezoelectric thin film. The piezoelectric thin film includes a perovskite type metal oxide, in which the perovskite type metal oxide is a mixed crystal system of at least a rhombohedral structure and a tetragonal structure, and a ratio between an a-axis lattice parameter and a c-axis lattice parameter of the tetragonal structure satisfies 1.15?c/a?1.30. The piezoelectric element includes on a substrate: the above-mentioned piezoelectric thin film; and a pair of electrodes provided in contact with the piezoelectric thin film.
    Type: Application
    Filed: February 28, 2011
    Publication date: December 20, 2012
    Applicants: KYOTO UNIVERSITY, CANON KABUSHIKI KAISHA
    Inventors: Makoto Kubota, Kenichi Takeda, Jumpei Hayashi, Mikio Shimada, Yuichi Shimakawa, Masaki Azuma, Yoshitaka Nakamura, Masanori Kawai
  • Publication number: 20120315710
    Abstract: In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S401) in which a reconstituted wafer is prepared by replacing defective chips with non-defective chips, a step (S403) in which the reconstituted wafer and the base wafer are connected to one another by laminating, a step (S406) in which through-electrodes are formed in the reconstituted wafer, and a step (S409) in which a separate reconstituted wafer is laminated onto and connected to the reconstituted wafer having through-electrodes.
    Type: Application
    Filed: February 1, 2011
    Publication date: December 13, 2012
    Inventors: Kazuyuki Hozawa, Kenichi Takeda, Mayu Aoki
  • Publication number: 20120256311
    Abstract: A bump electrode, a dummy bump, and a heat-resistant polymer film, whose upper-surface heights are uniformed, are formed on each of a first silicon substrate and a second silicon substrate, and then, the first silicon substrate and the second silicon substrate are bonded to each other so that the bump electrodes formed on the respective substrates are electrically connected to each other. At this time, the dummy bump is arranged so as to be bonded to the heat-resistant polymer film on the silicon substrate opposed thereto, so that a semiconductor device having both of good electrical connection between the bump electrodes and bump protection performance obtained by a polymer film with high heat resistance and without voids can be achieved.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 11, 2012
    Inventors: Kenichi TAKEDA, Mayu AOKI, Kazuyuki HOZAWA
  • Patent number: 8212649
    Abstract: A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: July 3, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Tsuyoshi Fujiwara, Toshinori Imai, Kenichi Takeda, Hiromi Shimamoto
  • Publication number: 20120135194
    Abstract: A high-viscosity material application device is provided with a discharge portion for discharging a high-viscosity material while moving relatively to a coating surface. The discharge portion includes a plurality of successive openings spaced in an application direction.
    Type: Application
    Filed: November 21, 2011
    Publication date: May 31, 2012
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Kenichi TAKEDA, Yoshiyuki Kumano
  • Patent number: 8174355
    Abstract: A resistor R1 formed by forming a first resistor layer 5a of 20 nm thickness including a tantalum nitride film at a concentration of nitrogen of less than 30 at % and a second resistor layer of 5 nm thickness including a tantalum nitride film at a concentration of nitrogen of 30 at % or more successively by a reactive DC sputtering method using tantalum as a sputtering target material and using a gas mixture of argon and nitrogen as a sputtering gas, and then fabricating the first and the second resistor layers, in which the resistance change ratio of the resistor can be suppressed to less than 1% even when a thermal load is applied in the interconnection step, by the provision of the upper region at a concentration of nitrogen of 30 at % or more.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: May 8, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Kenichi Takeda, Tsuyoshi Fujiwara, Toshinori Imai
  • Publication number: 20120098106
    Abstract: When a silicon through electrode is to be formed from a back surface (the surface on which a semiconductor device is not formed) of a silicon substrate, a wide range of an interlayer insulating film made of a Low-k material absorbs moisture, and there is a problem that the electrical characteristics of wiring are degraded. The above-described problem can be solved by forming at least a single ring-shaped frame laid out to enclose the silicon through electrode by using metal wirings in plural layers and a connection via connecting the upper and lower metal wirings in a Low-k material layer penetrated by the silicon through electrode and by forming a moisture barrier film made up of at least a metal wiring and a connection via between the silicon through electrode and a circuit wiring formed in the vicinity of the silicon through electrode.
    Type: Application
    Filed: July 1, 2009
    Publication date: April 26, 2012
    Inventors: Mayu Aoki, Kenichi Takeda, Kazuyuki Hozawa
  • Patent number: 8142678
    Abstract: A perovskite type oxide of a single crystal structure or a uniaxial-oriented crystal structure is represented by ABO3. Site A includes Pb as a main component and site B includes a plurality of elements. The perovskite type oxide includes a plurality of crystal phases selected from the group consisting of tetragonal, rhombohedral, orthorhombic, cubic, pseudo-cubic and monoclinic systems and the plurality of crystal phases are oriented in the direction of <100>.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: March 27, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takanori Matsuda, Katsumi Aoki, Toshihiro Ifuku, Kenichi Takeda, Tetsuro Fukui, Hiroshi Funakubo, Shintaro Yokoyama
  • Publication number: 20120068355
    Abstract: A semiconductor device including two silicon wafers stacked and bonded together with bumps of one wafer electrically coupled with those of the other wafer, in which generation of voids on the junction surface between the silicon wafers is suppressed. Due to a recess made in the surface of a buried conductive film, a cavity is formed in the junction surface between the silicon wafers. The ends of the cavity extend to the periphery of the junction surface between the silicon wafers. This allows the air trapped on the junction surface between the silicon wafers to get out through the cavity, thereby reducing the possibility of generation of voids on the junction surface.
    Type: Application
    Filed: July 7, 2011
    Publication date: March 22, 2012
    Inventors: Mayu Aoki, Kenichi Takeda, Kazuyuki Hozawa
  • Patent number: 8114307
    Abstract: The present invention provides a piezoelectric element and having a piezoelectric body and a pair of electrodes being contact with the piezoelectric body, wherein the piezoelectric body consists of an ABO3 perovskite oxide in which an A-site atom consists of Bi and a B-site atom is composed of an atom of at least two types of elements.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: February 14, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Katsumi Aoki, Kenichi Takeda, Tetsuro Fukui, Hiroshi Funakubo, Shintaro Yasui, Ken Nishida
  • Publication number: 20120032557
    Abstract: Provided is a vibration generating device in which more improvement of drive efficiency can be realized than conventional ones. The vibration generating device includes: a piezoelectric element including a piezoelectric material interposed between electrodes; a vibration member; a power source for applying an alternating voltage to the piezoelectric element; and a control section for controlling a frequency of the alternating voltage applied by the power source, in which the control section controls the frequency of the alternating voltage applied to the piezoelectric element so that the resonance frequency of the piezoelectric element is successively changed from low frequency side to high frequency side in a frequency range including a change range of a resonance frequency of the piezoelectric element.
    Type: Application
    Filed: July 5, 2011
    Publication date: February 9, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Tatsuo Furuta, Kenichi Takeda, Toshihiro Ifuku, Makoto Kubota, Hiroshi Saito
  • Publication number: 20120009756
    Abstract: A semiconductor device according to the present invention includes: a lower-surface oxidation preventing insulating film formed on a lower surface of a metal resistor element; an upper-surface oxidation preventing insulating film formed on an upper surface of the metal resistor element; and a side-surface oxidation preventing insulating film formed only near a side surface of the metal resistor element by performing anisotropic etching after being deposited on a whole surface of a wafer in a process separated from the lower-surface oxidation preventing insulating film and the upper-surface oxidation preventing insulating film. According to the present invention, it is possible to prevent the increase of the resistance value due to the oxidation of the metal resistor element and also to prevent the increase of the parasitic capacitance between metal wiring layers without complicating the fabrication process.
    Type: Application
    Filed: September 21, 2011
    Publication date: January 12, 2012
    Inventors: Tsuyoshi FUJIWARA, Toshinori IMAI, Kenichi TAKEDA, Hiromi SHIMAMOTO
  • Patent number: 8082640
    Abstract: A method for manufacturing a ferroelectric member element structure having a ferroelectric member film, and lower and upper electrodes between which the ferroelectric member film is sandwiched, includes the steps of: forming a buffer layer having pattern-shaped oriented growth on a monocrystal substrate; performing oriented growth of the lower electrode layer on the buffer layer; performing oriented growth of the ferroelectric member film to cover the buffer layer and the lower electrode layer; and removing a portion of the ferroelectric member film other than the portion having the oriented growth achieved along the pattern of the buffer layer, by means of an etching treatment.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: December 27, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenichi Takeda
  • Patent number: RE43660
    Abstract: The present invention provides a technology capable of achieving a highly-sensitive flow sensor, by forming a metal film having a relatively high TCR on a semiconductor substrate via an insulating film. A measurement device which is a thermal fluid flow sensor includes a heat element, resistance temperature detectors (upstream-side resistance temperature detector and downstream-side resistance temperature detector), and a resistance temperature detector for air which are all formed of a first metal film. The first metal film is formed of an ?-Ta film having a resistivity lower than three times the resistivity of a Ta ingot and obtained by deposition through sputtering on an amorphous film containing metal.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: September 18, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Noriyuki Sakuma, Naoki Yamamoto, Kenichi Takeda, Hiroshi Fukuda
  • Patent number: D705030
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: May 20, 2014
    Assignee: SMC Corporation
    Inventors: Chiaki Fukui, Youji Takakuwa, Kenichi Takeda