Abstract: A memory controller includes a layout setter and an access processor. The layout setter performs setting of data placement to be applied to multiple channels at the time of parallel data transfer between the memory controller and the flash memory using the multiple channels. The access processor performs, in performing access processing for data on the flash memory, the parallel data transfer to/from the flash memory using the data placement for the multiple channels set by the layout setter. In placing user data and parity data included in the data, the layout setter sets the data placement for the multiple channels to allow, in the multiple channels, second placement regions where the parity data are placed to be collectively placed forward or backward relative to first placement regions where the user data are placed, along an order of access at the time of the parallel data transfer.

Abstract: A memory controller includes a control circuit. The control circuit configures a plurality of physical blocks in a flash memory into a group. The control circuit allocates the plurality of physical blocks constituting the group to a data block and a redundant block. The control circuit writes data required to be saved into the data block. The control circuit writes redundant data based on the data required to be saved into the redundant block belonging to the same group as the data block. When all the data required to be saved are successfully written into the data block, the control circuit releases from the group at least one redundant block belonging to the same group as the data block.

Abstract: A memory controller includes a control circuit. The control circuit sets each block in a flash memory to an SLC mode or an MLC mode. The control circuit configures blocks set to the SLC mode into a first group. The control circuit configures blocks set to the MLC mode into a second group. The control circuit allocates the blocks constituting the first group to a first data block and a first redundant block. The control circuit allocates the blocks constituting the second group to a second data block and a second redundant block. The control circuit writes data required to be saved into the first data block. The control circuit writes first redundant data into the first redundant block. The control circuit writes replicated data of the data written into the first data block into the second data block. The control circuit writes second redundant data into the second redundant block.

Abstract: A memory controller capable of preventing important data stored in a flash memory from being lost and maintaining the quality of a physical block. A memory controller for controlling access to a flash memory including a plurality of physical blocks, each of which includes a plurality of pages, based on a command assigned from a host system. The memory controller stores a first correspondence relationship between a logical block of a first logical region and a physical block of a first physical region in a first storage unit. The memory controller manages the first physical region in which a process of moving data saved in the physical block of the first physical region having the correspondence relationship with the logical block of the first logical region is prohibited without being based on a command for writing the data to the first logical region assigned from the host system.

Abstract: A memory controller for preventing the storage area of a flash memory being reduced is provided. The memory controller controlling access to a flash memory based on a command provided from a host system, the memory controller includes: a processor, a RAM (random access memory), and a mask ROM (read only memory) in which a first firmware is written, wherein the memory controller is configured to: perform a search for a second firmware written in the flash memory based on the first firmware at a start-up time; and write a third firmware provided from the host system in the RAM when the second firmware is not found through the search and perform an initialization based on the third firmware written in the RAM.

Abstract: A memory controller includes a control circuit. The control circuit configures a plurality of physical blocks in a flash memory into a group. The control circuit allocates the plurality of physical blocks constituting the group to a data block and a redundant block. The control circuit writes data required to be saved into the data block. The control circuit writes redundant data based on the data required to be saved into the redundant block belonging to the same group as the data block. When all the data required to be saved are successfully written into the data block, the control circuit releases from the group at least one redundant block belonging to the same group as the data block.

Abstract: A memory controller includes a control circuit. The control circuit sets each block in a flash memory to an SLC mode or an MLC mode. The control circuit configures blocks set to the SLC mode into a first group. The control circuit configures blocks set to the MLC mode into a second group. The control circuit allocates the blocks constituting the first group to a first data block and a first redundant block. The control circuit allocates the blocks constituting the second group to a second data block and a second redundant block. The control circuit writes data required to be saved into the first data block. The control circuit writes first redundant data into the first redundant block. The control circuit writes replicated data of the data written into the first data block into the second data block. The control circuit writes second redundant data into the second redundant block.

Abstract: A memory controller controls access to a flash memory including a plurality of physical blocks, each of which includes a plurality of pages, based on a command assigned from a host system. The memory controller allocates a physical block within the flash memory in a prescribed search range as a prescribed physical block where management information is written, writes the management information necessary for accessing the flash memory to the prescribed physical block, and operates to search for the prescribed physical block when second firmware is read from the flash memory. The writing information, including the management information, is written to the prescribed physical block in a same format regardless of a type of flash memory. Information written to pages is sequentially read at prescribed page intervals in the prescribed search range in searching for the prescribed physical block.

Abstract: This memory controller controls access to a flash memory in response to commands from a host system. The memory controller identifies a physical block to be accessed among a plurality of physical blocks included in the flash memory, based on management information associated with each of the plurality of physical blocks. Furthermore, when data stored in one physical block among the plurality of physical blocks is transferred to a different physical block among the plurality of physical blocks that is different from the one physical block, the memory controller changes management information associated with the different physical block to management information associated with the one physical block.

Abstract: Disclosed herein a memory controller that controls data transfer between a host system and a flash memory. The memory controller is configured to execute background processing with a reduced throughput during a period during which processing corresponding to a command issued from the host system is not performed.

Abstract: To improve the versatility of a memory controller for controlling a plurality of types of flash memories.

Abstract: A memory controller capable of preventing important data stored in a flash memory from being lost and maintaining the quality of a physical block. A memory controller for controlling access to a flash memory including a plurality of physical blocks, each of which includes a plurality of pages, based on a command assigned from a host system. The memory controller stores a first correspondence relationship between a logical block of a first logical region and a physical block of a first physical region in a first storage unit. The memory controller manages the first physical region in which a process of moving data saved in the physical block of the first physical region having the correspondence relationship with the logical block of the first logical region is prohibited without being based on a command for writing the data to the first logical region assigned from the host system.

Abstract: A memory controller for preventing the storage area of a flash memory being reduced is provided. The memory controller controlling access to a flash memory based on a command provided from a host system, the memory controller includes: a processor, a RAM (random access memory), and a mask ROM (read only memory) in which a first firmware is written, wherein the memory controller is configured to: perform a search for a second firmware written in the flash memory based on the first firmware at a start-up time; and write a third firmware provided from the host system in the RAM when the second firmware is not found through the search and perform an initialization based on the third firmware written in the RAM.

Abstract: The memory controller comprises a storage unit in which the Registered-System-Max-NOE is registered per logical area and a processor which registers, in the storage unit, the System-Max-NOE (the maximum value of multiple erasures respectively corresponded to multiple physical areas) at the time when allocating a spare physical area in one of the logical areas as the Registered-System-Max-NOE to be associated with the allocation destination logical area. The processor performs a wear leveling processing based on the Registered-System-Max-NOE per logical area.

Abstract: The memory controller comprises a storage unit in which the Registered-System-Max-NOE is registered per logical area and a processor which registers, in the storage unit, the System-Max-NOE (the maximum value of multiple erasures respectively corresponded to multiple physical areas) at the time when allocating a spare physical area in one of the logical areas as the Registered-System-Max-NOE to be associated with the allocation destination logical area. The processor performs a wear leveling processing based on the Registered-System-Max-NOE per logical area.