Abstract: A method of and apparatus for efficiently transferring data between a memory system and an instruction processor having a dedicated cache memory. A read request within the instruction processor for a data element not currently stored within the dedicated cache memory creates a read cache miss condition. A transfer of the eight word block containing the requested data element is initiated from the memory system beginning with the 72 bit double word containing the requested data element. The eight word block of data is placed into a block buffer upon being received by the instruction processor. The instruction processor is permitted to resume instruction execution and access to the cache memory as soon as the requested data element has been received by the block buffer. The eight word data block is transferred from the block buffer to cache memory at the next read cache miss condition.

Abstract: A data protection and correction scheme is implemented by providing main and shadow stores for groups of data bits from a segmented data word. The data bits are divided into even and odd address groups for storage into even and odd storage sections. Each group of 3 bits from a 36-bit data word is supplied in uncomplemented form to even and odd address main stores and in a complemented form to even and odd address shadow stores. By storing the complemented parity bit with the uncomplemented data and the uncomplemented parity bit with the complemented data, the odd parity of the input data is converted to an even parity which may be checked upon read-out from the main store. If this parity test fails, the shadow store is accessed to supply the correct data. When a write address and a read address attempt to access the same storage address a conflict is detected and input data and parity are directly supplied to an output multiplexor.

Abstract: A system for detecting failures in a cache memory stores data words that may represent instructions or operands in plurality of blocks. The data words are divided into a plurality of data bit groups. A tag memory is associated with each block of data words in the cache memory. Storage in the cache memory is directed by block address bits, and storage in the tag memory is directed by tag address bits. A first parity generator is coupled to the cache memory which generates address parity bits selected from block and tag address bits. A second parity generator provides data parity bits for each group of the data word bits. These two parity bits are combined and are stored along with the bit groups of the associated data word. Upon read-out of a data word, the stored combined parity bits are compared with parity bits that were generated from the selected address bits and data bits and error indication occurs when a parity error results.