Patents by Inventor Kenichi Yasuda
Kenichi Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230371175Abstract: To prevent interfacial peeling due to the stress of an insulating layer in a capacitor-inductor integrated electronic component having three or more conductor layers. An electronic component includes: a conductor layer M1 including a conductor pattern constituting an inductor; a conductor pattern overlapping a part of the conductor pattern through a dielectric film; an insulating layer covering the conductor layer M1 and conductor pattern; a conductor layer M2 provided on the insulating layer and including a conductor pattern constituting the inductor; and an insulating layer covering the conductor layer M2. The conductor layer M2 is formed to be branching from or independently of the conductor pattern and further includes a dummy pattern overlapping the conductor pattern. This prevents the stress of the insulating layer from being directly applied to the conductor pattern to thereby prevent peeling at the interface between the conductor layer M1 and the dielectric film.Type: ApplicationFiled: September 13, 2021Publication date: November 16, 2023Inventors: Yu FUKAE, Tomoya HANAI, Yusuke OBA, Kenichi YOSHIDA, Katsuharu YASUDA, Takashi OHTSUKA
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Publication number: 20230356220Abstract: The present disclosure provides a channel device (100, 101, 102, 103, 200, 300, 500, 600, 700) including a flow channel (10) formed of a groove (31) provided in a substrate (30) and a porous membrane (50) having pores (56) communicating in a direction intersecting a thickness direction thereof, in which at least a portion of the porous membrane (50) in contact with the substrate (30) is liquid-tightly sealed along the flow channel (10), and a manufacturing method thereof.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Inventors: Aya MOCHIZUKI, Hiroyuki YUKAWA, Kenichi YASUDA, Takahiro OBA
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Patent number: 11693620Abstract: An information processing apparatus comprises a first acquiring unit configured to acquire a command input to application software, a second acquiring unit configured to acquire scene information representing a scene represented by a screen displayed when executing the application software, a third acquiring unit configured to acquire a command file based on the command and the scene information, and an execution unit configured to execute processing in accordance with the command file.Type: GrantFiled: March 10, 2020Date of Patent: July 4, 2023Assignee: Humming Heads, Inc.Inventors: Naoyuki Oe, Takuma Sugita, Makoto Kurita, Yuichi Yasuda, Shogo Otsuka, Kenichi Yasuda
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Publication number: 20230171726Abstract: In performing wireless communication between terminals to perform time difference measurement and propagation time measurement, first and second terminals that transmit a signal at least once in attempting space-time synchronization are included. The first terminal measures a reception phase of a locally transmitted signal, and a reception phase of a signal transmitted by the second terminal, adds a positive or negative phase to the measured reception phase, and makes a report to the second terminal. The second terminal measures a reception phase of a locally transmitted signal, and a reception phase of a signal transmitted by the first terminal, and makes a report to the first terminal. The first and second terminals obtain a time difference or propagation time according to a reception phase measured by a local device and reported from a counterpart, and obtain additional information based on a phase reflected in the time difference or propagation time.Type: ApplicationFiled: November 29, 2021Publication date: June 1, 2023Applicant: NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGYInventors: Maki YOSHIDA, Nobuyasu SHIGA, Satoshi YASUDA, Kenichi TAKIZAWA
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Publication number: 20220228108Abstract: There is provided a cell culture base material having a porous membrane having an opening ratio of 30% to 70% and an extracellular matrix with which an inside of a hole of the porous membrane is filled. There is also provided a cell culture base material with cells having a cell layer on at least one surface of the cell culture base material.Type: ApplicationFiled: April 8, 2022Publication date: July 21, 2022Inventors: Keisuke OKU, Daichi HIKIMOTO, Takahiro OBA, Kenichi YASUDA, Hiroyuki YUKAWA
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Patent number: 11213945Abstract: A robot simulator includes a storage device that stores model information related to the robot and an obstacle in the vicinity of the robot, and an acquisition device that obtains first input information defining a start position and an end position of operation of the robot. A processing device generates a path for moving the distal end portion of the robot from the start position to the end position while avoiding collisions between the robot and the obstacle based on the first input information and the model information. The processing device also generates image data including an illustration of the obstacle and an index indicating a via-point of the path.Type: GrantFiled: February 19, 2018Date of Patent: January 4, 2022Inventors: Koichi Kuwahara, Yoshifumi Onoyama, Kenichi Yasuda, Wataru Watanabe
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Patent number: 11200945Abstract: A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.Type: GrantFiled: January 31, 2017Date of Patent: December 14, 2021Assignee: ZENTEL JAPAN CORPORATIONInventors: Takashi Kubo, Masaru Haraguchi, Takeshi Hamamoto, Kenichi Yasuda, Yasuhiko Tsukikawa, Hironori Iga
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Patent number: 11123864Abstract: A motion teaching apparatus includes a teaching motion detection device, a demonstration tool, and circuitry. A robot includes a leading end to move in a first coordinate system. A teaching motion detection device detects a position of the demonstration tool in a second coordinate system. The circuitry derives a relationship between the first and second coordinate system based on a position of the demonstration tool in the first coordinate system at at least one spot and based on the position of the demonstration tool in the second coordinate system at the at least one spot; obtains a transition of the position of the demonstration tool during the demonstration using the demonstration tool; and generates a motion command to control motion of the leading end of the robot based on the transition and the coordinate system relationship information.Type: GrantFiled: July 2, 2019Date of Patent: September 21, 2021Assignee: KABUSHIKI KAISHA YASKAWA DENKIInventors: Toshihiro Iwasa, Ryoichi Nagai, Nathanael Mullennix, Shingo Ando, Kenichi Yasuda
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Patent number: 10991418Abstract: A control device of the invention for a semiconductor memory device comprising an interface conforming to JEDEC standard of DDRx-SDRAM or LPDDRx-SDRAM, comprises banks, a read/write control circuit, and a transfer control circuit. Each bank comprises subarrays. Each subarray comprises memory cells arranged along bit lines and word lines. The read/write control circuit controls reading of data from and writing of data to the semiconductor memory device. The transfer control circuit controls data transfer inside the semiconductor memory device and sets to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface.Type: GrantFiled: March 6, 2017Date of Patent: April 27, 2021Assignee: ZENTEL JAPAN CORPORATIONInventors: Masaru Haraguchi, Takashi Kubo, Yasuhiko Tsukikawa, Hironori Iga, Kenichi Yasuda, Takeshi Hamamoto
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Publication number: 20200293275Abstract: An information processing apparatus comprises a first acquiring unit configured to acquire a command input to application software, a second acquiring unit configured to acquire scene information representing a scene represented by a screen displayed when executing the application software, a third acquiring unit configured to acquire a command file based on the command and the scene information, and an execution unit configured to execute processing in accordance with the command file.Type: ApplicationFiled: March 10, 2020Publication date: September 17, 2020Inventors: Naoyuki OE, Takuma Sugita, Makoto Kurita, Yuichi Yasuda, Shogo Otsuka, Kenichi Yasuda
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Publication number: 20200135261Abstract: According to a control device of a first aspect of the invention, for a semiconductor memory device comprising an interface conforming to JEDEC (Joint Electron Device Engineering Council) standard of DDRx-SDRAM or LPDDRx-SDRAM, the control device comprises a plurality of banks, a read/write control circuit, and a transfer control circuit. The banks are connected to one another by an internal data bus, and each bank, separated from one another by at least one sense amplifier row comprising a plurality of sense amplifiers, comprises a plurality of subarrays. Each subarray comprises a plurality of memory cells arranged along a plurality of bit lines and a plurality of word lines orthogonal to the bit lines. The read/write control circuit controls reading of data from the semiconductor memory device and writing of data to the semiconductor memory device.Type: ApplicationFiled: March 6, 2017Publication date: April 30, 2020Inventors: Masaru Haraguchi, Takashi Kubo, Yasuhiko Tsukikawa, Hironori Iga, Kenichi Yasuda, Takeshi Hamamoto
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Publication number: 20200001454Abstract: A motion teaching apparatus includes a teaching motion detection device, a demonstration tool, and circuitry. A robot includes a leading end to move in a first coordinate system. A teaching motion detection device detects a position of the demonstration tool in a second coordinate system. The circuitry derives a relationship between the first and second coordinate system based on a position of the demonstration tool in the first coordinate system at at least one spot and based on the position of the demonstration tool in the second coordinate system at the at least one spot; obtains a transition of the position of the demonstration tool during the demonstration using the demonstration tool; and generates a motion command to control motion of the leading end of the robot based on the transition and the coordinate system relationship information.Type: ApplicationFiled: July 2, 2019Publication date: January 2, 2020Applicant: KABUSHIKI KAISHA YASKAWA DENKIInventors: Toshihiro IWASA, Ryoichi NAGAI, Nathanael MULLENNIX, Shingo ANDO, Kenichi YASUDA
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Publication number: 20190378561Abstract: A plurality of memory cells are arranged along a plurality of bit lines and a plurality of word lines. A sense amplifier is connected to each of the bit lines. Arranged along each bit line are at least four memory cells including first to fourth memory cells that are either connected to or disconnected from one of the bit lines by means of first to fourth switching elements according to an active or inactive state of first to fourth word lines. The first memory cell stores a first bit value, the second memory cell stores a second bit value, and the third and fourth memory cells each store a third bit value. A memory cell array control circuit activates and then deactivates the third and fourth word lines, subsequently activates the first and second word lines, and then activates the sense amplifier.Type: ApplicationFiled: January 31, 2017Publication date: December 12, 2019Inventors: TAKASHI KUBO, MASARU HARAGUCHI, TAKESHI HAMAMOTO, KENICHI YASUDA, YASUHIKO TSUKIKAWA, HIRONORI IGA
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Publication number: 20180236657Abstract: A robot simulator includes a storage device that stores model information related to the robot and an obstacle in the vicinity of the robot, and an acquisition device that obtains first input information defining a start position and an end position of operation of the robot. A processing device generates a path for moving the distal end portion of the robot from the start position to the end position while avoiding collisions between the robot and the obstacle based on the first input information and the model information. The processing device also generates image data including an illustration of the obstacle and an index indicating a via-point of the path.Type: ApplicationFiled: February 19, 2018Publication date: August 23, 2018Applicant: KABUSHIKI KAISHA YASKAWA DENKIInventors: Koichi KUWAHARA, Yoshifumi ONOYAMA, Kenichi YASUDA, Wataru WATANABE
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Patent number: 9881874Abstract: According to one embodiment, a forming method of superposition checking marks includes forming a first superposition checking mark to have a first step with respect to an arrangement surface for the first superposition checking mark, forming an opaque film having a second step resulting from the first step on the arrangement surface, and forming on the opaque film a second superposition checking mark provided with a transparent film allowing observation of the second step.Type: GrantFiled: March 1, 2016Date of Patent: January 30, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kenichi Yasuda, Shinya Arai
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Publication number: 20170154852Abstract: According to one embodiment, a forming method of superposition checking marks includes forming a first superposition checking mark to have a first step with respect to an arrangement surface for the first superposition checking mark, forming an opaque film having a second step resulting from the first step on the arrangement surface, and forming on the opaque film a second superposition checking mark provided with a transparent film allowing observation of the second step.Type: ApplicationFiled: March 1, 2016Publication date: June 1, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Kenichi YASUDA, Shinya ARAI
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Publication number: 20150192704Abstract: The method for producing an optical film includes a film-curing step of curing the coating to form a liquid crystal layer by supporting a second surface of the transparent support by a back-up roller while heating, and irradiating the coating with ultraviolet light, wherein, when an reaching temperature of the transparent support in curing of the coating is set to 80° C. or higher, and P [N/m2] represents a surface pressure, T [N] represents a tensile force applied to the transparent support, R [m] represents a radius of the back-up roller, L [m] represents a width of the transparent support, and G [GPa] represents an elastic modulus in a width direction of the transparent support at the reaching temperature of the transparent support in curing of the coating, Expression (1): P=T/RL and Expression (2): P>69/(G?1.5)+400 are satisfied.Type: ApplicationFiled: January 5, 2015Publication date: July 9, 2015Applicant: FUJIFILM CorporationInventors: Kenichi YASUDA, Hiroyuki YUKAWA, Yuki SAIKI
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Patent number: 8883263Abstract: A coated film manufacturing method and a coating machine are provided which can prevent deformation of a die coater due to evaporation of a coating liquid and prevent surface deficiency occurring when starting the coating. A coating machine is prepared which includes a die coater having a manifold, a slot communicating with the manifold, and a lip face formed at an end of the slot, a heat-insulating plate being disposed in a region below the lip face of the die coater and having a tapered top end portion, and a depressurizing chamber being disposed upstream in a web conveying direction from the die coater. The coating machine is made to stand by at a position for forming a clearance greater than a predetermined clearance between the coating machine and the web at the time of coating while flowing the coating liquid from the die coater.Type: GrantFiled: October 26, 2011Date of Patent: November 11, 2014Assignee: FUJIFILM CorporationInventors: Kenichi Yasuda, Kimio Yukawa, Ryousuke Shimizu, Noriaki Horikawa
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Patent number: 8846139Abstract: A coating apparatus includes: a slot die configured to apply coating solution on a support by discharging the coating solution from a tip of a slot and forming a coating solution bead in a clearance between the tip of the slot and the support; a pipe through which the coating solution is fed to a pocket of the slot die; an orifice formed in the pipe at a position nearer a circumference of a circular cross section in a radial direction of the pipe in relation to a center of the circular cross section; a forward tapered inlet channel which is formed at an entrance side of the orifice in the pipe and whose aperture narrows to the orifice; a rearward tapered outlet channel which is formed at an exit side of the orifice in the pipe and whose aperture grows toward a downstream.Type: GrantFiled: January 14, 2011Date of Patent: September 30, 2014Assignee: Fujifilm CorporationInventors: Kenichi Yasuda, Ryousuke Shimizu, Kazuhiro Oki
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Patent number: 8420178Abstract: A liquid sending method comprises the steps of sending a coating solution to a liquid sending pipe, passing the coating solution to an orifice which is provided at a part of the liquid sending pipe to prevent a vibration propagation and passing the coating solution to a pulsation absorb device which is provided at a part of the liquid sending pipe where is located at a downstream of the orifice, wherein the pulsation absorb device includes a first chamber that a liquid can flow in and out, a second chamber which is introduced a gas, and a diaphragm which separates the first chamber and the second chamber.Type: GrantFiled: September 22, 2009Date of Patent: April 16, 2013Assignee: Fujifilm CorporationInventors: Kenichi Yasuda, Hitoshi Satou, Kazuhiro Oki