Patents by Inventor Kenichiro Yoshii

Kenichiro Yoshii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180039523
    Abstract: An information processing system includes a first core, a second core having a processing speed that is slower than the first core, a first memory, a second memory having a slower response time than the first memory, and a management processor. The management processor is configured to determine a core for executing a task, cause program data for executing the task to be copied to the first memory and then cause the first core to execute the task using the program data in the first memory, when the first core is determined as the core for executing the task, and cause the program data for executing the task to be copied to the second memory and then cause the second core to execute the task using the program data in the second memory, when the second core is determined as the core for executing the task.
    Type: Application
    Filed: February 21, 2017
    Publication date: February 8, 2018
    Inventors: Takayuki AKAMINE, Kenichiro YOSHII, Hiroshi YAO
  • Patent number: 9864548
    Abstract: According to one embodiment, a memory module includes a volatile memory, a nonvolatile memory, and a controller. The volatile memory is data readable and writable. The nonvolatile memory is data readable and writable and stores therein correspondence information containing an attribute indicating any of volatile, nonvolatile, and both of volatile and nonvolatile associated with an address in an address space assigned to the volatile memory and the nonvolatile memory. The controller reads data from and writes data to the volatile memory or the nonvolatile memory, referring to the correspondence information.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: January 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shoji Sawamura, Nobuhiro Kondo, Kenichi Maeda, Kenichiro Yoshii
  • Publication number: 20170263301
    Abstract: A storage device includes a memory cell array, a voltage detector disposed to detect a voltage of power supplied to the memory cell array, and a controller. The controller is configured to carry out reading of data from a target memory cell and then rewriting of the data in the target memory cell, if the detected voltage is above a threshold when a prompt of a read operation with respect to the target memory cell occurs, and prohibit the reading operation from being started, if the detected voltage is below the threshold when the prompt occurs.
    Type: Application
    Filed: December 19, 2016
    Publication date: September 14, 2017
    Inventors: Hiroshi SUKEGAWA, Yoshihiro UEDA, Kenichiro YOSHII
  • Publication number: 20170262377
    Abstract: According to one embodiment, when the first command is received from a host, a controller translates a first address designated by a first command into a second address representing a real address of the nonvolatile memory based on a first mapping and accesses the translated second address of the nonvolatile memory. The controller determines whether or not the first mapping is changed based on a degree of wear of the nonvolatile memory and changes some of all the correspondence relations in a case where the first mapping is changed.
    Type: Application
    Filed: September 1, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Hiroshi Yao
  • Patent number: 9690691
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: June 27, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Publication number: 20170103017
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Application
    Filed: December 8, 2016
    Publication date: April 13, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro FUKUTOMI, Kenichiro YOSHII, Shinichi KANNO, Shigehiro ASANO
  • Publication number: 20170075630
    Abstract: According to one embodiment, a memory module includes a volatile memory, a nonvolatile memory, and a controller. The volatile memory is data readable and writable. The nonvolatile memory is data readable and writable and stores therein correspondence information containing an attribute indicating any of volatile, nonvolatile, and both of volatile and nonvolatile associated with an address in an address space assigned to the volatile memory and the nonvolatile memory. The controller reads data from and writes data to the volatile memory or the nonvolatile memory, referring to the correspondence information.
    Type: Application
    Filed: March 4, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shoji SAWAMURA, Nobuhiro Kondo, Kenichi Maeda, Kenichiro Yoshii
  • Patent number: 9569303
    Abstract: According to one embodiment, an information processing apparatus includes a host and a memory system. The memory system includes a nonvolatile memory. The host includes a volatile memory, a first host control unit, and a second host control unit. The volatile memory includes a first area to be used by the host and a second area as a cache memory to temporarily store data of the nonvolatile memory. The first host control unit computes a first code, and stores the first data and the first code in the second area. The first code is redundant information of the first data. The second host control unit reads second data and a second code from the second area, performs error detection on the second data based on the second code, and transfers the second data. The second code is redundant information of the second data.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Maeda, Nobuhiro Kondo, Kenichiro Yoshii, Satoshi Kaburaki
  • Publication number: 20160259576
    Abstract: According to one embodiment, a nonvolatile memory system includes a memory including a first memory and a second memory, the first memory including memory strings, the memory strings including memory cell transistors connected in series; and a memory controller which compresses a failure string position information of the first memory, which stores the compressed failure string position information in the second memory, and which decompresses the compressed failure string position information stored in the second memory.
    Type: Application
    Filed: September 8, 2015
    Publication date: September 8, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shohei ASAMI, Tokumasa HARA, Hiroshi YAO, Kenichiro YOSHII, Riki SUZUKI, Toshikatsu HIDA, Osamu TORII
  • Publication number: 20160247581
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a memory interface, a storage unit which stores defective memory cell information, and a storage location control unit which creates second data of a second data length longer than a first data length based on an area at a write destination of first data of the first data length, causes the memory interface to write a plurality of second data to the nonvolatile memory, causes the memory interface to read the second data corresponding to the first data instructed to be read from the nonvolatile memory, and restores the first data based on the read second data and the defective memory cell information.
    Type: Application
    Filed: September 9, 2015
    Publication date: August 25, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Riki SUZUKI, Toshikatsu Hida, Tokumasa Hara, Kenichiro Yoshii, Youhei Kouchi, Norikazu Yoshida
  • Patent number: 9396141
    Abstract: According to embodiments a memory system is connectable to a host which includes a host controller and a host memory including a first memory area and a second memory area. The memory system includes an interface unit, a non-volatile memory, and a controller unit. The interface unit receives a read command and a write command. The controller unit writes write-data to the non-volatile memory according to the write command. The controller unit determines whether read-data requested by the read command is in the first memory area. If the read-data is in the first memory area, the controller unit causes the host controller to copy the read-data from the first memory area to the second memory area. If the read-data is not in the first memory area, the controller unit reads the read-data from the non-volatile memory and causes the host controller to store the read-data in the second memory area.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: July 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Maeda, Nobuhiro Kondo, Kenichiro Yoshii, Keigo Hara, Toshio Fujisawa
  • Publication number: 20160054943
    Abstract: According to one embodiment, an information processing apparatus includes a memory system and a host. The memory system includes a nonvolatile first memory and a first control unit. The host includes a volatile second memory and a second control unit. The second memory includes a first area which is used by the host and a second area which is used by the memory system. The second control unit transmits an access request to the first control unit. The access request contains an address. The first control unit determines whether an access destination is the first memory or the second area based on the address and accesses the determined access destination.
    Type: Application
    Filed: March 3, 2015
    Publication date: February 25, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro YOSHII, Kenichi MAEDA, Nobuhiro KONDO
  • Publication number: 20160041871
    Abstract: According to one embodiment, an information processing apparatus includes a host and a memory system. The memory system includes a nonvolatile memory. The host includes a volatile memory, a first host control unit, and a second host control unit. The volatile memory includes a first area to be used by the host and a second area as a cache memory to temporarily store data of the nonvolatile memory. The first host control unit computes a first code, and stores the first data and the first code in the second area. The first code is redundant information of the first data. The second host control unit reads second data and a second code from the second area, performs error detection on the second data based on the second code, and transfers the second data. The second code is redundant information of the second data.
    Type: Application
    Filed: February 27, 2015
    Publication date: February 11, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichi MAEDA, Nobuhiro KONDO, Kenichiro YOSHII, Satoshi KABURAKI
  • Publication number: 20160034221
    Abstract: According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state.
    Type: Application
    Filed: March 6, 2015
    Publication date: February 4, 2016
    Inventors: Tatsuya Zettsu, Katsuhiko Ueki, Yoshihisa Kojima, Hiroshi Yao, Kenichiro Yoshii, Ikuo Magaki
  • Patent number: 9165685
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: October 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro Asano, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
  • Publication number: 20150261444
    Abstract: According to one embodiment, a memory system includes a first memory, an interface, and a control unit. The first memory can operate in first mode in which n (n?2) pieces of unit data are written per word line and in second mode in which one piece of unit data is written per word line. When n pieces of unit data to be written to the first word line exist in the second memory, the control unit writes the first unit data to the first word line, using the n pieces of unit data to be written to the first word line. When receiving a flush request, the control unit writes a second unit data to a second word line, the second unit data being unit data stored in the second memory, based on the second mode.
    Type: Application
    Filed: July 18, 2014
    Publication date: September 17, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro YOSHII, Naomi TAKEDA, Hiroshi YAO, Nobuhiro KONDO
  • Patent number: 9136020
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: September 15, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro Asano, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
  • Patent number: 9003261
    Abstract: A memory system includes a first nonvolatile memory, a second nonvolatile memory with a longer access latency than the first nonvolatile memory, a first error correction unit, a second error correction unit, and an interface. The first nonvolatile memory stores first data and a first error correction code generated for the first data. The second nonvolatile memory stores a second error correction code which is generated for the first data with a higher correction ability than that of the first error correction code. The first error correction unit performs error correction on the first data by using the first error correction code. The second error correction unit performs error correction on the first data by using the second error correction code. The interface transmits the first data after the error correction to a host.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ikuo Magaki, Naoto Oshiyama, Kenichiro Yoshii, Kosuke Hatsuda, Shirou Fujita, Tokumasa Hara, Kohei Oikawa, Kenta Yasufuku
  • Publication number: 20150067237
    Abstract: According to one embodiment, a memory controller includes an address translation information storage unit that stores plural translation information formed by classifying a correspondence between a logical address and a physical address into two or more hierarchies, a tag management unit that sores a cache line tag, which includes hierarchy information corresponding to each of the translation information stored in the translation information storage unit, and a control unit that identities whether the translation information is stored in the translation information storage unit or not by using a cache line tag.
    Type: Application
    Filed: February 28, 2014
    Publication date: March 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro YOSHII, Konosuke WATANABE, Naoto OSHIYAMA, Satoshi KABURAKI
  • Publication number: 20150046634
    Abstract: According to embodiments a memory system is connectable to a host which includes a host controller and a host memory including a first memory area and a second memory area. The memory system includes an interface unit, a non-volatile memory, and a controller unit. The interface unit receives a read command and a write command. The controller unit writes write-data to the non-volatile memory according to the write command. The controller unit determines whether read-data requested by the read command is in the first memory area. If the read-data is in the first memory area, the controller unit causes the host controller to copy the read-data from the first memory area to the second memory area. If the read-data is not in the first memory area, the controller unit reads the read-data from the non-volatile memory and causes the host controller to store the read-data in the second memory area.
    Type: Application
    Filed: March 7, 2014
    Publication date: February 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichi MAEDA, Nobuhiro Kondo, Kenichiro Yoshii, Keigo Hara, Toshio Fujisawa