Patents by Inventor Kenichiro Yoshii

Kenichiro Yoshii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8879349
    Abstract: A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: November 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Ikuo Magaki, Naoto Oshiyama, Tokumasa Hara, Akira Yamaga, Ryo Yamaki, Kenta Yasufuku, Naomi Takeda, Yu Nakanishi, Arata Miyamoto, Naoaki Kokubun, Daisuke Iwai
  • Publication number: 20140310575
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
    Type: Application
    Filed: June 24, 2014
    Publication date: October 16, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigehiro ASANO, Kenichiro YOSHII, Kazuhiro FUKUTOMI, Shinichi KANNO
  • Publication number: 20140310576
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
    Type: Application
    Filed: June 24, 2014
    Publication date: October 16, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigehiro ASANO, Kenichiro YOSHII, Kazuhiro FUKUTOMI, Shinichi KANNO
  • Publication number: 20140241096
    Abstract: A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.
    Type: Application
    Filed: August 6, 2013
    Publication date: August 28, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro YOSHII, Ikuo MAGAKI, Naoto OSHIYAMA, Tokumasa HARA, Akira YAMAGA, Ryo YAMAKI, Kenta YASUFUKU, Naomi TAKEDA, Yu NAKANISHI, Arata MIYAMOTO, Naoaki KOKUBUN, Daisuke IWAI
  • Patent number: 8788900
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro Asano, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
  • Publication number: 20140129901
    Abstract: A memory system includes a first nonvolatile memory, a second nonvolatile memory with a longer access latency than the first nonvolatile memory, a first error correction unit, a second error correction unit, and an interface. The first nonvolatile memory stores first data and a first error correction code generated for the first data. The second nonvolatile memory stores a second error correction code which is generated for the first data with a higher correction ability than that of the first error correction code. The first error correction unit performs error correction on the first data by using the first error correction code. The second error correction unit performs error correction on the first data by using the second error correction code. The interface transmits the first data after the error correction to a host.
    Type: Application
    Filed: September 3, 2013
    Publication date: May 8, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ikuo MAGAKI, Naoto OSHIYAMA, Kenichiro YOSHII, Kosuke HATSUDA, Shirou FUJITA, Tokumasa HARA, Kohei OIKAWA, Kenta YASUFUKU
  • Publication number: 20140068378
    Abstract: According to an embodiment, a semiconductor storage device includes a memory, an encoding unit that generates a parity, and a decoding unit that includes a syndrome calculating unit, an error position polynomial calculating unit, and an error searching and correcting unit, and performs an error correcting process based on data and the parity read from the memory. At the time of performing a compaction process, a process of the error searching and correcting unit is not performed, when the number of error bits acquired by an error position polynomial is equal to or less than a first threshold value based on valid data.
    Type: Application
    Filed: February 21, 2013
    Publication date: March 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro YOSHII, Naoaki Kokubun, Naoto Oshiyama, Ryo Yamaki, Ikuo Magaki, Kenta Yasufuku, Akira Yamaga
  • Patent number: 8612721
    Abstract: According to one embodiment, upon request from an information processor, a semiconductor storage controller writes pieces of data in predetermined units into storage locations in which no data has been written in erased areas within a semiconductor chip's storage area. A third table and a second table which is a subset thereof include physical addresses each indicating a storage location of each of pieces of the data within the semiconductor chip. The first table includes either information specifying a second table entry or information specifying a third table entry. The semiconductor storage controller records the first and the second tables into a volatile memory or records the first table into a volatile memory and the third table into a nonvolatile memory.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: December 17, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro Asano, Shinichi Kanno, Kenichiro Yoshii
  • Publication number: 20130297900
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Application
    Filed: July 2, 2013
    Publication date: November 7, 2013
    Inventors: Kazuhiro FUKUTOMI, Kenichiro YOSHII, Shinichi KANNO, Shigehiro ASANO
  • Publication number: 20130232391
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
    Type: Application
    Filed: April 23, 2013
    Publication date: September 5, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shigehiro ASANO, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
  • Patent number: 8516182
    Abstract: A controller includes a storage for a translation table showing logical and physical addresses in a flash memory in correspondence with one another; another storage storing FAT information indicating the state of data stored in each of pages contained in each of blocks and FAT information identifiers each identifying a block to which pages each storing therein the data in the state indicated by the FAT information belong, while keeping them in correspondence with one another; yet another storage for a block management table showing block identifiers, use-state judging information indicating whether the corresponding block is used/unused, and the FAT information identifiers corresponding to all the blocks indicated as being used by the use-state judging information, while keeping them in correspondence with one another; and a controller controlling unit managing data stored in the flash memory by using the translation table, the FAT information, and the block management table.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: August 20, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Patent number: 8495651
    Abstract: An information processing system periodically performs a real-time operation including a plurality of chained tasks. The system includes a plurality of processors, a unit for dividing the chained tasks into a first task group and a second task group based on a relationship in order of execution among the tasks, the second task group being executed after the first task group, and a unit for performing a scheduling operation of periodically assigning each of the first task group and the second task group to at least one of the processors to periodically execute the first task group at regular time intervals and periodically execute the second task group at the regular time intervals with a one-period delay relative to the first task group.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: July 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Hirokuni Yano, Kenichiro Yoshii
  • Patent number: 8495336
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: July 23, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Patent number: 8453033
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips having writable storage regions in which data is written. The data has one or more pieces of first data, and one or more pieces of the first data includes second data. The device includes a determining unit that determines a prescribed number or fewer of semiconductor memory chips to which the first data is written; a write controller that writes the the first data and redundant information calculated from the second data and used for correcting an error in the second data into the writable storage regions in the determined semiconductor memory chips; and a storage unit that stores identification information and region specifying information associated with each other.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: May 28, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno, Shigehiro Asano
  • Patent number: 8448034
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: May 21, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro Asano, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
  • Patent number: 8397017
    Abstract: A volatile management memory stores management information for managing a use state of a storage medium. A management information storing unit divides the management information into plural division pieces and individually stores them in the storage medium. A main controller receives a command from a host device while the division pieces are being stored, performs data processing for the storage medium in response to the command between each division piece is stored, updates the management information divided into the division pieces according to the data processing content, and creates a log representing an update content of the management information. A log storing unit stores the log in the storage medium. A restoring unit reads the division pieces stored in the storage medium to the management memory as the management information, updates the management information according to the log stored in the storage medium, and restores the updated management information.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: March 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno, Shigehiro Asano
  • Patent number: 8392476
    Abstract: According to one embodiment, a semiconductor memory device performs writing of data to a semiconductor memory element in response to a request to write the data with a specified logical block address from a host and performs writing of valid data to the semiconductor memory element for compaction according to a log-structured method. The semiconductor memory device adjusts a frequency of the writing response to a request from the host and a frequency of the writing for compaction according to a predetermined ratio.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro Asano, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
  • Patent number: 8219767
    Abstract: A information processing apparatus includes, upon instructing for writing back stored contents of a main memory unit to the stored contents of the main memory unit at the time of previous modification in a sequence number that is used for identifying whether write back to the main memory unit is needed, from a backup data stored in a backup memory unit, the sequence number stored in a sequence number memory unit. The information processing apparatus selects the backup data including an integrity verification data indicating that writing is carried out completely. The information processing apparatus extracts an original data and a write destination address included in the selected backup data and writes the original data, for each original data and the write address extracted from the backup data, to a storage area, of the main memory unit, indicated by the write destination address.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: July 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Hiroshi Yao, Tomohide Jokan, Tatsunori Kanai
  • Patent number: 8171477
    Abstract: An information processing system performs a real-time operation including a combination of a plurality of tasks. The system includes a plurality of processors, a unit which stores structural description information and a plurality of programs describing procedures corresponding to the tasks, the structural description information indicating a relationship in input/output between the programs and including cost information concerning time required for executing each of the programs, a unit which determines an execution start timing and execution term of each of a plurality of threads for execution of the programs based on the structural description information, and a unit which performs a scheduling operation of assigning the threads to at least one of the processors according to a result of the determining.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: May 1, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Kenichiro Yoshii, Hirokuni Yano
  • Publication number: 20120072644
    Abstract: According to one embodiment, upon request from an information processor, a semiconductor storage controller writes pieces of data in predetermined units into storage locations in which no data has been written in erased areas within a semiconductor chip's storage area. A third table and a second table which is a subset thereof include physical addresses each indicating a storage location of each of pieces of the data within the semiconductor chip. The first table includes either information specifying a second table entry or information specifying a third table entry. The semiconductor storage controller records the first and the second tables into a volatile memory or records the first table into a volatile memory and the third table into a nonvolatile memory.
    Type: Application
    Filed: March 1, 2011
    Publication date: March 22, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro ASANO, Shinichi Kanno, Kenichiro Yoshii