Patents by Inventor Kenichiro Yoshii

Kenichiro Yoshii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8087020
    Abstract: An information processing system performs a real-time operation periodically at specific time intervals. The system includes a unit for performing a scheduling operation of assigning the real-time operation to a processor to perform the real-time operation periodically at the specific time intervals by the processor, a unit for computing a ratio of an execution time of the real-time operation to be performed by the processor at a first operating speed, based on the specific time intervals and cost information concerning a time required to perform the real-time operation by the processor at the first operating speed, and a unit for performing an operating speed control operation to operate the processor at a second operating speed that is lower than the first operating speed, the second operating speed being determined based on the computed ratio.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: December 27, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Hirokuni Yano, Kenichiro Yoshii
  • Patent number: 8060925
    Abstract: A processor communicating with a first memory configured to store first information and first data, and communicating with a second memory configured to store second information and second data, includes a computing unit configured to perform computation using the first data and the second data; an storing unit configured integrally with the computing unit to store first authentication information and second authentication information; a reading unit configured to read out the first information and the second information; an authenticating unit configured to authenticate the first memory by comparing the first information and the first authentication information, and to authenticate the second memory by comparing the second information and the second authentication information; and an controlling unit configured to control an access of the computing unit to the first memory and the second memory based on a result of the authentications.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: November 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Tatsunori Kanai
  • Publication number: 20110231624
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Application
    Filed: September 16, 2010
    Publication date: September 22, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuhiro FUKUTOMI, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Publication number: 20110214033
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips having writable storage regions in which data is written. The data has one or more pieces of first data, and one or more pieces of the first data includes second data. The device includes a determining unit that determines a prescribed number or fewer of semiconductor memory chips to which the first data is written; a write controller that writes the the first data and redundant information calculated from the second data and used for correcting an error in the second data into the writable storage regions in the determined semiconductor memory chips; and a storage unit that stores identification information and region specifying information associated with each other.
    Type: Application
    Filed: September 20, 2010
    Publication date: September 1, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno, Shigehiro Asano
  • Publication number: 20110202812
    Abstract: According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written.
    Type: Application
    Filed: September 23, 2010
    Publication date: August 18, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro ASANO, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
  • Publication number: 20110202578
    Abstract: According to one embodiment, a semiconductor memory device performs writing of data to a semiconductor memory element in response to a request to write the data with a specified logical block address from a host and performs writing of valid data to the semiconductor memory element for compaction according to a log-structured method. The semiconductor memory device adjusts a frequency of the writing response to a request from the host and a frequency of the writing for compaction according to a predetermined ratio.
    Type: Application
    Filed: September 20, 2010
    Publication date: August 18, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigehiro ASANO, Kenichiro Yoshii, Kazuhiro Fukutomi, Shinichi Kanno
  • Patent number: 7971014
    Abstract: In an information processing apparatus, when an instruction is issued to write back storage contents of a main memory unit that is non-volatile, data and a write destination address included in a backup data that is set with a read permission are extracted from the backup data stored in a backup memory unit that is non-volatile. Further, according to the data and the write destination address extracted from the backup data, the data is written to a storage area of the main-memory unit indicated by the write destination address.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Hiroshi Yao, Tomohide Jokan, Tatsunori Kanai
  • Publication number: 20110060864
    Abstract: A volatile management memory stores management information for managing a use state of a storage medium. A management information storing unit divides the management information into plural division pieces and individually stores them in the storage medium. A main controller receives a command from a host device while the division pieces are being stored, performs data processing for the storage medium in response to the command between each division piece is stored, updates the management information divided into the division pieces according to the data processing content, and creates a log representing an update content of the management information. A log storing unit stores the log in the storage medium. A restoring unit reads the division pieces stored in the storage medium to the management memory as the management information, updates the management information according to the log stored in the storage medium, and restores the updated management information.
    Type: Application
    Filed: March 15, 2010
    Publication date: March 10, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenichiro YOSHII, Kazuhiro Fukutomi, Shinichi Kanno, Shigehiro Asano
  • Publication number: 20100241819
    Abstract: A controller includes a storage for a translation table showing logical and physical addresses in a flash memory in correspondence with one another; another storage storing FAT information indicating the state of data stored in each of pages contained in each of blocks and FAT information identifiers each identifying a block to which pages each storing therein the data in the state indicated by the FAT information belong, while keeping them in correspondence with one another; yet another storage for a block management table showing block identifiers, use-state judging information indicating whether the corresponding block is used/unused, and the FAT information identifiers corresponding to all the blocks indicated as being used by the use-state judging information, while keeping them in correspondence with one another; and a controller controlling unit managing data stored in the flash memory by using the translation table, the FAT information, and the block management table.
    Type: Application
    Filed: September 4, 2009
    Publication date: September 23, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenichiro YOSHII, Shinichi Kanno, Shigehiro Asano
  • Patent number: 7761779
    Abstract: An access control apparatus includes a parity generator that generates a parity for original data to be written into a memory; and a parity adder that generates parity-added data by adding the parity to the original data; a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data. The first syndrome is a value associated beforehand with a first access code to be used when a writer accesses the memory. The apparatus also includes a first mask generator that generates the first mask data based on the first syndrome, the first access code, and a first memory address; a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data; and a writing unit that writes the first post-operation data into the memory.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: July 20, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Kenichiro Yoshii
  • Patent number: 7739457
    Abstract: An information processing system includes a first processor having a first local memory, a second processor having a second local memory, and a third processor having a third local memory. The system further includes a unit which maps one of the second and third local memories in part of an effective address space of a first thread to be executed by the first processor. The mapped one of the second and third local memories is the local memory of a corresponding one of the second and third processors, which executes a second thread interacting with the first thread. The system also includes a unit that changes a local memory to be mapped in part of the effective address space of the first thread from the one of the second and third local memories to the other.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Kenichiro Yoshii
  • Patent number: 7730249
    Abstract: In a device control apparatus, a processor that operates according to software, an OS storage unit stores Operating Systems that operate on the processor, and a storage unit stores privileged software which operates on the processor. The privileged software calls one of the Operating Systems when the processor receives an interrupt from a device, and the Operating System controls the device. Furthermore, a detecting unit detects an interrupt to the processor, a judging unit judges whether the Operating System has called the privileged software from the storage unit in a first predetermined time from detection of the interrupt, and a resetting unit resets the processor when the judging unit judges that the Operating Systcm 9em has not called the privileged software from the storage unit.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: June 1, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Tatsunori Kanai, Hiroshi Yao
  • Patent number: 7685599
    Abstract: An information processing system performs a plurality of tasks within a specific time interval. The system includes a bus, a plurality of processors which transfer data via the bus, and a unit for performing a scheduling operation of determining execution start timing of each of the tasks and at least one the processors which executes the tasks, based on cost information concerning a time required to perform each of the tasks and bandwidth information concerning a data transfer bandwidth required by each of the tasks, to perform the tasks within the specific time interval without overlapping execution terms of at least two tasks of the tasks, the two tasks requiring data transfer bandwidths not less than those of the others of the tasks.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: March 23, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Hirokuni Yano, Kenichiro Yoshii
  • Patent number: 7657890
    Abstract: A real-time processing system that executes a plurality of threads, each of the threads being a unit of execution of a real-time operation, comprises a plurality of processors, a unit which selects a tightly coupled thread group from among the threads based on coupling attribute information indicative of a coupling attribute between the threads, the tightly coupled thread group including a set of tightly coupled threads running in cooperation with each other, and a unit which performs a scheduling operation of dispatching the tightly coupled threads to several of the processors that are equal to the tightly coupled threads to simultaneously execute the tightly coupled threads by the several of the processors.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: February 2, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Kenichiro Yoshii, Hirokuni Yano
  • Patent number: 7653861
    Abstract: An access control apparatus includes a writer syndrome generator that generates a writer syndrome of writer mask data to mask the parity-added data, the writer syndrome being associated with a writer access ID used when a writer that requests writing of the write data in the memory accesses the memory; a write mask generator that generates the writer mask data based on the writer syndrome, the writer access ID, and a write address in the memory at which the writer writes the write data; a first XOR calculator that obtains first post-operation data by calculating an XOR between the parity-added data and the writer mask data; and a write address converter that converts the write address into another address determined by the writer access ID.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: January 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Kenichiro Yoshii
  • Patent number: 7636765
    Abstract: In a data transfer scheme using a caching technique and/or a compression technique which is capable of reducing the network load of a network connecting between data transfer devices, correspondences between data and their names are registered at the data transfer devices and the corresponding names are transferred, instead of transferring the data, for those data for which the correspondences are registered, so that it is possible to reduce the amount of transfer data among the data transfer devices.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: December 22, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Toshibumi Seki, Kenichiro Yoshii, Hideaki Sato, Takayuki Miyazawa, Haruhiko Toyama, Yasuhiro Kimura, Hideki Yoshida
  • Publication number: 20090172325
    Abstract: In an information processing apparatus, when an instruction is issued to write back storage contents of a main memory unit that is non-volatile, data and a write destination address included in a backup data that is set with a read permission are extracted from the backup data stored in a backup memory unit that is non-volatile. Further, according to the data and the write destination address extracted from the backup data, the data is written to a storage area of the main-memory unit indicated by the write destination address.
    Type: Application
    Filed: August 26, 2008
    Publication date: July 2, 2009
    Inventors: Kenichiro YOSHII, Hiroshi YAO, Tomohide JOKAN, Tatsunori KANAI
  • Publication number: 20090164743
    Abstract: A information processing apparatus includes, upon instructing for writing back stored contents of a main memory unit to the stored contents of the main memory unit at the time of previous modification in a sequence number that is used for identifying whether write back to the main memory unit is needed, from a backup data stored in a backup memory unit, the sequence number stored in a sequence number memory unit. The information processing apparatus selects the backup data including an integrity verification data indicating that writing is carried out completely. The information processing apparatus extracts an original data and a write destination address included in the selected backup data and writes the original data, for each original data and the write address extracted from the backup data, to a storage area, of the main memory unit, indicated by the write destination address.
    Type: Application
    Filed: August 27, 2008
    Publication date: June 25, 2009
    Inventors: Kenichiro YOSHII, Hiroshi Yao, Tomohide Jokan, Tatsunori Kanai
  • Publication number: 20090044188
    Abstract: An information processing system performs a real-time operation periodically at specific time intervals. The system includes a unit for performing a scheduling operation of assigning the real-time operation to a processor to perform the real-time operation periodically at the specific time intervals by the processor, a unit for computing a ratio of an execution time of the real-time operation to be performed by the processor at a first operating speed, based on the specific time intervals and cost information concerning a time required to perform the real-time operation by the processor at the first operating speed, and a unit for performing an operating speed control operation to operate the processor at a second operating speed that is lower than the first operating speed, the second operating speed being determined based on the computed ratio.
    Type: Application
    Filed: October 8, 2008
    Publication date: February 12, 2009
    Inventors: Tatsunori KANAI, Seiji MAEDA, Hirokuni YANO, Kenichiro YOSHII
  • Patent number: 7480731
    Abstract: In a data transfer scheme using a caching technique and/or a compression technique which is capable of reducing the network load of a network connecting between data transfer devices, correspondences between data and their names are registered at the data transfer devices and the corresponding names are transferred, instead of transferring the data, for those data for which the correspondences are registered, so that it is possible to reduce the amount of transfer data among the data transfer devices. Server side data transfer devices and client side data transfer devices can be provided in multiple-to-one, one-to-multiple, or multiple-to-multiple manners.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: January 20, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshibumi Seki, Tatsunori Kanai, Kenichiro Yoshii, Hideki Yoshida, Haruhiko Toyama, Hideaki Sato, Yasuhiro Kimura, Takayuki Miyazawa