Patents by Inventor Kenichiro Yoshii

Kenichiro Yoshii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7761779
    Abstract: An access control apparatus includes a parity generator that generates a parity for original data to be written into a memory; and a parity adder that generates parity-added data by adding the parity to the original data; a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data. The first syndrome is a value associated beforehand with a first access code to be used when a writer accesses the memory. The apparatus also includes a first mask generator that generates the first mask data based on the first syndrome, the first access code, and a first memory address; a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data; and a writing unit that writes the first post-operation data into the memory.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: July 20, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Kenichiro Yoshii
  • Patent number: 7739457
    Abstract: An information processing system includes a first processor having a first local memory, a second processor having a second local memory, and a third processor having a third local memory. The system further includes a unit which maps one of the second and third local memories in part of an effective address space of a first thread to be executed by the first processor. The mapped one of the second and third local memories is the local memory of a corresponding one of the second and third processors, which executes a second thread interacting with the first thread. The system also includes a unit that changes a local memory to be mapped in part of the effective address space of the first thread from the one of the second and third local memories to the other.
    Type: Grant
    Filed: May 22, 2007
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Kenichiro Yoshii
  • Patent number: 7730249
    Abstract: In a device control apparatus, a processor that operates according to software, an OS storage unit stores Operating Systems that operate on the processor, and a storage unit stores privileged software which operates on the processor. The privileged software calls one of the Operating Systems when the processor receives an interrupt from a device, and the Operating System controls the device. Furthermore, a detecting unit detects an interrupt to the processor, a judging unit judges whether the Operating System has called the privileged software from the storage unit in a first predetermined time from detection of the interrupt, and a resetting unit resets the processor when the judging unit judges that the Operating Systcm 9em has not called the privileged software from the storage unit.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: June 1, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichiro Yoshii, Tatsunori Kanai, Hiroshi Yao
  • Patent number: 7685599
    Abstract: An information processing system performs a plurality of tasks within a specific time interval. The system includes a bus, a plurality of processors which transfer data via the bus, and a unit for performing a scheduling operation of determining execution start timing of each of the tasks and at least one the processors which executes the tasks, based on cost information concerning a time required to perform each of the tasks and bandwidth information concerning a data transfer bandwidth required by each of the tasks, to perform the tasks within the specific time interval without overlapping execution terms of at least two tasks of the tasks, the two tasks requiring data transfer bandwidths not less than those of the others of the tasks.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: March 23, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Hirokuni Yano, Kenichiro Yoshii
  • Patent number: 7657890
    Abstract: A real-time processing system that executes a plurality of threads, each of the threads being a unit of execution of a real-time operation, comprises a plurality of processors, a unit which selects a tightly coupled thread group from among the threads based on coupling attribute information indicative of a coupling attribute between the threads, the tightly coupled thread group including a set of tightly coupled threads running in cooperation with each other, and a unit which performs a scheduling operation of dispatching the tightly coupled threads to several of the processors that are equal to the tightly coupled threads to simultaneously execute the tightly coupled threads by the several of the processors.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: February 2, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Kenichiro Yoshii, Hirokuni Yano
  • Patent number: 7653861
    Abstract: An access control apparatus includes a writer syndrome generator that generates a writer syndrome of writer mask data to mask the parity-added data, the writer syndrome being associated with a writer access ID used when a writer that requests writing of the write data in the memory accesses the memory; a write mask generator that generates the writer mask data based on the writer syndrome, the writer access ID, and a write address in the memory at which the writer writes the write data; a first XOR calculator that obtains first post-operation data by calculating an XOR between the parity-added data and the writer mask data; and a write address converter that converts the write address into another address determined by the writer access ID.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: January 26, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Kenichiro Yoshii
  • Patent number: 7636765
    Abstract: In a data transfer scheme using a caching technique and/or a compression technique which is capable of reducing the network load of a network connecting between data transfer devices, correspondences between data and their names are registered at the data transfer devices and the corresponding names are transferred, instead of transferring the data, for those data for which the correspondences are registered, so that it is possible to reduce the amount of transfer data among the data transfer devices.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: December 22, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Toshibumi Seki, Kenichiro Yoshii, Hideaki Sato, Takayuki Miyazawa, Haruhiko Toyama, Yasuhiro Kimura, Hideki Yoshida
  • Publication number: 20090172325
    Abstract: In an information processing apparatus, when an instruction is issued to write back storage contents of a main memory unit that is non-volatile, data and a write destination address included in a backup data that is set with a read permission are extracted from the backup data stored in a backup memory unit that is non-volatile. Further, according to the data and the write destination address extracted from the backup data, the data is written to a storage area of the main-memory unit indicated by the write destination address.
    Type: Application
    Filed: August 26, 2008
    Publication date: July 2, 2009
    Inventors: Kenichiro YOSHII, Hiroshi YAO, Tomohide JOKAN, Tatsunori KANAI
  • Publication number: 20090164743
    Abstract: A information processing apparatus includes, upon instructing for writing back stored contents of a main memory unit to the stored contents of the main memory unit at the time of previous modification in a sequence number that is used for identifying whether write back to the main memory unit is needed, from a backup data stored in a backup memory unit, the sequence number stored in a sequence number memory unit. The information processing apparatus selects the backup data including an integrity verification data indicating that writing is carried out completely. The information processing apparatus extracts an original data and a write destination address included in the selected backup data and writes the original data, for each original data and the write address extracted from the backup data, to a storage area, of the main memory unit, indicated by the write destination address.
    Type: Application
    Filed: August 27, 2008
    Publication date: June 25, 2009
    Inventors: Kenichiro YOSHII, Hiroshi Yao, Tomohide Jokan, Tatsunori Kanai
  • Publication number: 20090044188
    Abstract: An information processing system performs a real-time operation periodically at specific time intervals. The system includes a unit for performing a scheduling operation of assigning the real-time operation to a processor to perform the real-time operation periodically at the specific time intervals by the processor, a unit for computing a ratio of an execution time of the real-time operation to be performed by the processor at a first operating speed, based on the specific time intervals and cost information concerning a time required to perform the real-time operation by the processor at the first operating speed, and a unit for performing an operating speed control operation to operate the processor at a second operating speed that is lower than the first operating speed, the second operating speed being determined based on the computed ratio.
    Type: Application
    Filed: October 8, 2008
    Publication date: February 12, 2009
    Inventors: Tatsunori KANAI, Seiji MAEDA, Hirokuni YANO, Kenichiro YOSHII
  • Patent number: 7480731
    Abstract: In a data transfer scheme using a caching technique and/or a compression technique which is capable of reducing the network load of a network connecting between data transfer devices, correspondences between data and their names are registered at the data transfer devices and the corresponding names are transferred, instead of transferring the data, for those data for which the correspondences are registered, so that it is possible to reduce the amount of transfer data among the data transfer devices. Server side data transfer devices and client side data transfer devices can be provided in multiple-to-one, one-to-multiple, or multiple-to-multiple manners.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: January 20, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshibumi Seki, Tatsunori Kanai, Kenichiro Yoshii, Hideki Yoshida, Haruhiko Toyama, Hideaki Sato, Yasuhiro Kimura, Takayuki Miyazawa
  • Patent number: 7464379
    Abstract: An information processing system performs a real-time operation periodically at specific time intervals. The system includes a unit for performing a scheduling operation of assigning the real-time operation to a processor to perform the real-time operation periodically at the specific time intervals by the processor, a unit for computing a ratio of an execution time of the real-time operation to be performed by the processor at a first operating speed, based on the specific time intervals and cost information concerning a time required to perform the real-time operation by the processor at the first operating speed, and a unit for performing an operating speed control operation to operate the processor at a second operating speed that is lower than the first operating speed, the second operating speed being determined based on the computed ratio.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: December 9, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Hirokuni Yano, Kenichiro Yoshii
  • Publication number: 20080282249
    Abstract: An information processing system performs a real-time operation including a combination of a plurality of tasks. The system includes a plurality of processors, a unit which stores structural description information and a plurality of programs describing procedures corresponding to the tasks, the structural description information indicating a relationship in input/output between the programs and including cost information concerning time required for executing each of the programs, a unit which determines an execution start timing and execution term of each of a plurality of threads for execution of the programs based on the structural description information, and a unit which performs a scheduling operation of assigning the threads to at least one of the processors according to a result of the determining.
    Type: Application
    Filed: July 14, 2008
    Publication date: November 13, 2008
    Inventors: Tatsunori Kanai, Seiji Maeda, Kenichiro Yoshii, Hirokuni Yano
  • Patent number: 7441248
    Abstract: In a data transfer device, presence/absence of a prescribed header in the received request message is analyzed, and information indicating the presence/absence of the prescribed header, or information indicating either presence or absence of the prescribed header when the prescribed header is either present or absent as a result of analysis is stored. Then, when a reply message corresponding to the request message is received, the presence/absence of the prescribed header is checked by referring to the stored information, and the reply message is transferred according to a result of checking.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: October 21, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Sato, Tatsunori Kanai, Hideki Yoshida, Toshibumi Seki, Kenichiro Yoshii, Takayuki Miyazawa, Yasuhiro Kimura, Haruhiko Toyama
  • Publication number: 20080250119
    Abstract: In a data transfer scheme using a caching technique and/or a compression technique which is capable of reducing the network load of a network connecting between data transfer devices, correspondences between data and their names are registered at the data transfer devices and the corresponding names are transferred, instead of transferring the data, for those data for which the correspondences are registered, so that it is possible to reduce the amount of transfer data among the data transfer devices. Even when the name corresponding to the data is not registered so that it is impossible to transfer the corresponding name instead of transferring the data, it is possible to reduce the amount of transfer data among the data transfer devices by transferring the compressed data in which this data is expressed in a compressed form by utilizing the name corresponding to the registered reference data.
    Type: Application
    Filed: December 31, 2007
    Publication date: October 9, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsunori KANAI, Toshibumi Seki, Kenichiro Yoshii, Hideaki Sato, Takayuki Miyazawa, Haruhiko Toyama, Yasuhiro Kimura, Hideki Yoshida
  • Publication number: 20080244229
    Abstract: In an information processing apparatus, a fetch to a storage address of a first storage unit which stores a first instruction executed at first within a plurality of instructions that is included in a software and executed when a processor starts the software via the channel is detected. It is detected that the processor executed a specific instruction within the plurality of instructions via the channel. It is determined whether a predetermined time has passed since the detection of the fetch to the storage address until the detection of the execution of the specific instruction. When it is determined that the predetermined time has not passed, it is determined whether an interrupt to the processor is prohibited based on a result of the processor executing the specific instruction, and an access is released to the process according to a result of determination.
    Type: Application
    Filed: September 17, 2007
    Publication date: October 2, 2008
    Inventors: Hiroshi Yao, Kenichiro Yoshii, Tatsunori Kanai
  • Patent number: 7418705
    Abstract: An information processing system performs a real-time operation including a combination of a plurality of tasks. The system includes a plurality of processors, a unit which stores structural description information and a plurality of programs describing procedures corresponding to the tasks, the structural description information indicating a relationship in input/output between the programs and including cost information concerning time required for executing each of the programs, a unit which determines an execution start timing and execution term of each of a plurality of threads for execution of the programs based on the structural description information, and a unit which performs a scheduling operation of assigning the threads to at least one of the processors according to a result of the determining.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: August 26, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Seiji Maeda, Kenichiro Yoshii, Hirokuni Yano
  • Publication number: 20080189434
    Abstract: In a data transfer scheme using a caching technique and/or a compression technique which is capable of reducing the network load of a network connecting between data transfer devices, correspondences between data and their names are registered at the data transfer devices and the corresponding names are transferred, instead of transferring the data, for those data for which the correspondences are registered, so that it is possible to reduce the amount of transfer data among the data transfer devices. Server side data transfer devices and client side data transfer devices can be provided in multiple-to-one, one-to-multiple, or multiple-to-multiple manners.
    Type: Application
    Filed: March 31, 2008
    Publication date: August 7, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshibumi Seki, Tatsunori Kanai, Kenichiro Yoshii, Hideki Yoshida, Haruhiko Toyama, Hideaki Sato, Yasuhiro Kimura, Takayuki Miyazawa
  • Publication number: 20080183845
    Abstract: In a client server system, the network load is reduced by using the fingerprint compression and the differential compression, by providing the proxy server at the server side and using the general purpose browser at the client side, without requiring a separate proxy server at the client side. The client downloads and installs a fingerprint cache processing engine as a plug-in.
    Type: Application
    Filed: October 16, 2007
    Publication date: July 31, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuichi KOBA, Yasuhiro KIMURA, Kenichiro YOSHII, Atsushi SHONO, Hideaki SATO, Toshibumi SEKI
  • Publication number: 20080178261
    Abstract: An information processing apparatus includes a storage unit, a processor, a channel, a detecting unit, and a control unit. The storage unit stores therein privilege software that is allowed to access a first access range. The processor executes the privilege software and software that is allowed to access a second access range. The channel connects the storage unit and the processor. The detecting unit detects a fetch request that is issued by the processor through the channel and specifies an address at which the privilege software is stored. The control unit controls an access range of the processor based on whether the fetch request is detected.
    Type: Application
    Filed: September 6, 2007
    Publication date: July 24, 2008
    Inventors: Hiroshi Yao, Tatsunori Kanai, Kenichiro Yoshii