Patents by Inventor Kenji Kawabata

Kenji Kawabata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240081718
    Abstract: A biological information measurement device includes a sensor unit that detects predetermined biological information related to an organ of a living body, an A/D conversion unit that converts a measurement signal output from the sensor unit into a digital signal, a storage unit that stores information including a digital signal related to the measurement signal output from the A/D conversion unit, an analysis processing unit that determines presence or absence of a suspicion of an abnormality in the organ by analyzing the digital signal, and a measurement control unit that changes a sampling frequency related to A/D conversion of the measurement signal under a predetermined condition when the analysis processing unit has determined that a suspicion of an abnormality is present in the organ.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Kenji FUJII, Yasuhiro KAWABATA, Naomi MATSUMURA, Akito ITO, Yuki SAKAGUCHI, Daizo OKA, Takuya YOSHIDA, Seiji FUKUNAGA, Tatsuaki OKA
  • Publication number: 20240076754
    Abstract: A molten iron refining method having, an auxiliary material, and an oxidizing gas supplied through a top-blowing lance, to a cold iron source and molten pig iron that are contained/fed in a converter-type vessel, and molten iron is subjected to a refining process. A pre-charged cold iron source is charged into the converter-type vessel at an amount not larger than 0.15 times. A furnace-top-added cold iron source that's part or all of the cold iron source and added from a furnace top is fed during the refining process. A burner at a leading end of the top-blowing lance that spray holes through which a fuel and a combustion-supporting gas are ejected. During the refining process, a powdery auxiliary material processed into powder that's part of the auxiliary material is blown in, to pass through a flame formed by the burner.
    Type: Application
    Filed: December 21, 2021
    Publication date: March 7, 2024
    Applicant: JFE STEEL CORPORATION
    Inventors: Futoshi OGASAWARA, Hidemitsu NEGISHI, Kenji NAKASE, Shota AMANO, Yumi MURAKAMI, Rei YOKOMORI, Yudai HATTORI, Ryo KAWABATA, Naoki KIKUCHI
  • Patent number: 11329349
    Abstract: A polyolefin micro porous film includes at least one of polyethylene and polypropylene, in which the compressive elastic modulus is 95 MPa or more and 150 MPa or less, the surface roughness (Ra) of a film surface is measured for a front surface and a rear surface, and the average value (Ra(ave)) thereof is 0.01 ?m to 0.30 ?m.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: May 10, 2022
    Assignee: Ube Industries, Ltd.
    Inventors: Ryo Sakimoto, Kenji Kawabata, Hiroki Nagumo, Taiga Adachi
  • Patent number: 11139533
    Abstract: A polyolefin micro-porous film containing a polypropylene resin, in which a meltdown temperature of the polyolefin micro-porous film is 195° C. to 230° C. A weight-average molecular weight of the polypropylene resin is 500,000 to 800,000. Furthermore, a molecular weight distribution of the polypropylene resin is 7.5 to 16.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: October 5, 2021
    Assignee: Ube Industries, Ltd.
    Inventors: Toru Kidosaki, Ryo Sakimoto, Kenji Kawabata
  • Publication number: 20190157647
    Abstract: A polyolefin micro-porous film containing a polypropylene resin, in which a meltdown temperature of the polyolefin micro-porous film is 195° C. to 230° C. A weight-average molecular weight of the polypropylene resin is 500,000 to 800,000. Furthermore, a molecular weight distribution of the polypropylene resin is 7.5 to 16.
    Type: Application
    Filed: February 7, 2017
    Publication date: May 23, 2019
    Inventors: Toru KIDOSAKI, Ryo SAKIMOTO, Kenji KAWABATA
  • Publication number: 20180175353
    Abstract: A polyolefin micro porous film includes at least one of polyethylene and polypropylene, in which the compressive elastic modulus is 95 MPa or more and 150 MPa or less, the surface roughness (Ra) of a film surface is measured for a front surface and a rear surface, and the average value (Ra(ave)) thereof is 0.01 ?m to 0.30 ?m.
    Type: Application
    Filed: June 17, 2016
    Publication date: June 21, 2018
    Inventors: Ryo SAKIMOTO, Kenji KAWABATA, Hiroki NAGUMO, Taiga ADACHI
  • Publication number: 20170009203
    Abstract: Disclosed are: a gene transduction method for use in the induction of the differentiation of stem cells such as ES cells or iPS cells into hepatocytes effectively; stem cells into each of which a gene useful for the induction of the differentiation into hepatocytes is introduced; and hepatocytes produced from stem cells each having the gene introduced therein. A specific gene can be introduced into stem cells such as ES cells or iPS cells using an adenovirus vector. The effective induction of the differentiation into hepatocytes can be achieved by introducing the gene. Specifically, the effective induction of the differentiation of stem cells such as ES cells or iPS cells into hepatocytes can be achieved by introducing at least one gene selected from HEX gene, HNF4A gene, HNF6 gene and SOX17 gene into the stem cells.
    Type: Application
    Filed: September 16, 2016
    Publication date: January 12, 2017
    Applicant: Japan Health Sciences Foundation
    Inventors: Hiroyuki Mizuguchi, Kenji Kawabata, Mitsuru Inamura, Miho Furue
  • Publication number: 20160046904
    Abstract: Provided is a method of stably maintaining and culturing “hepatoblast-like cells” generated during a differentiation-inducing process from pluripotent stem cells to hepatocytes. The present invention also provides a culture product obtained by the culture method. The hepatoblast-like cells can be maintained and cultured stably by bringing a laminin into contact with the hepatoblast-like cells. The method of the present invention which uses a laminin makes it possible for the first time to culture, maintain, and proliferate the hepatoblast-like cells. Desired mature cells such as mature hepatocytes and bile duct epithelial cells can be generated in a short time period and can be acquired at a desired timing by maintaining the hepatoblast-like cells. Further, the resulting cultured hepatoblast-like cells were demonstrated to be capable of being induced to differentiate into mature hepatocytes, mature cholangiocytes, bile duct epithelial cells, and the like.
    Type: Application
    Filed: April 8, 2014
    Publication date: February 18, 2016
    Inventors: Hiroyuki MIZUGUCHI, Kenji KAWABATA, Kazuo TAKAYAMA, Kiyotoshi SEKIGUCHI
  • Publication number: 20150344567
    Abstract: The present invention provides a monoclonal antibody that recognizes a lipid substance on an iPS cell surface and an ES cell surface as an epitope, and does not recognize EC cells, the antibody having a cytotoxic activity against a target cell, a method of producing a uniform differentiated cell population free of an undifferentiated cell, including contacting a cell population differentiated from an iPS or ES cell with the above antibody, and recovering viable cells, an agent for a cell transplantation therapy, containing a differentiated cell population obtained by the method, and the like.
    Type: Application
    Filed: December 20, 2013
    Publication date: December 3, 2015
    Inventors: Toshisuke KAWASAKI, Nobuko KAWASAKI, Miho FURUE, Kenji KAWABATA, Hidenao TOYODA
  • Patent number: 9183673
    Abstract: In accordance with an embodiment, a simulation apparatus includes a two-dimensional section dividing processing unit, a two-dimensional simulator, a one-dimensional combining processing unit, and a three-dimensional shape combining processing unit. The two-dimensional section dividing processing unit divides a three-dimensional shape as a simulation target into at least one set of two-dimensional sections intersecting with each other and defines the three-dimensional shape as the two-dimensional sections. The two-dimensional simulator runs a two-dimensional shape simulation in each time step for each of the two-dimensional sections obtained by the dividing and acquires a two-dimensional shape. The one-dimensional combining processing unit extracts a film configuration for each intersection of the two-dimensional sections from the acquired two-dimensional shape and combines the film configurations to acquire one-dimensional film configurations.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: November 10, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ai Omodaka, Yoshiyuki Shioyama, Kenji Kawabata
  • Publication number: 20150014899
    Abstract: A method includes: a laminate block preparing step of preparing a laminate block as an assembly of a number of laminates, by alternately laminating magnetic layers containing, as their main constituent, a magnetic metal material containing a glass material and conductor layers containing a conductive material so that the conductor layers are electrically connected to each other to form a coil pattern; a dividing step of dividing the laminate block by cutting the laminate block for each of the laminates; a magnetic material applying step of applying a magnetic material containing the magnetic metal material to side surfaces of the laminates; and a firing step of firing the laminates with the magnetic material applied thereto, thereby preparing a component body. This achieves a method for manufacturing a laminated coil component preferred for a power inductor with improved reliability, without impairing direct-current superimposition characteristics.
    Type: Application
    Filed: October 1, 2014
    Publication date: January 15, 2015
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Kunihiko HAMADA, Eiichi MAEDA, Kenji KAWABATA
  • Publication number: 20140236337
    Abstract: In accordance with an embodiment, a pattern inspection method includes modeling a shape simulation of a pattern, performing in-line measurement with respect to control parameters which are to be controlled in a manufacturing process of the pattern, executing the shape simulation by using a result of the in-line measurement, and judging acceptance of a pattern shape based on a result of the shape simulation.
    Type: Application
    Filed: August 30, 2013
    Publication date: August 21, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kenji Kawabata, Toru Koike, Kenichi Kadota
  • Publication number: 20140063010
    Abstract: In accordance with an embodiment, a simulation apparatus includes a two-dimensional section dividing processing unit, a two-dimensional simulator, a one-dimensional combining processing unit, and a three-dimensional shape combining processing unit. The two-dimensional section dividing processing unit divides a three-dimensional shape as a simulation target into at least one set of two-dimensional sections intersecting with each other and defines the three-dimensional shape as the two-dimensional sections. The two-dimensional simulator runs a two-dimensional shape simulation in each time step for each of the two-dimensional sections obtained by the dividing and acquires a two-dimensional shape. The one-dimensional combining processing unit extracts a film configuration for each intersection of the two-dimensional sections from the acquired two-dimensional shape and combines the film configurations to acquire one-dimensional film configurations.
    Type: Application
    Filed: December 5, 2012
    Publication date: March 6, 2014
    Inventors: Ai OMODAKA, Yoshiyuki SHIOYAMA, Kenji KAWABATA
  • Patent number: 8456908
    Abstract: A multi-dot flash memory includes active areas arranged in a first direction, which extend to a second direction crossed to the first direction, the first and second direction being parallel to a surface of a semiconductor substrate, floating gates arranged in the first direction, which are provided above the active areas, a word line provided above the floating gates, which extends to the first direction, and bit lines provided between the floating gates, which extend to the second direction. Each of the floating gates has two side surfaces in the first direction, shapes of the two side surfaces are different from each other, and shapes of the facing surfaces of the floating gates which are adjacent to each other in the first direction are symmetrical.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: June 4, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Ichikawa, Hiroshi Watanabe, Kenji Kawabata
  • Publication number: 20120231490
    Abstract: Disclosed are: a gene transduction method for use in the induction of the differentiation of stem cells such as ES cells or iPS cells into hepatocytes effectively; stem cells into each of which a gene useful for the induction of the differentiation into hepatocytes is introduced; and hepatocytes produced from stem cells each having the gene introduced therein. A specific gene can be introduced into stem cells such as ES cells or iPS cells using an adenovirus vector. The effective induction of the differentiation into hepatocytes can be achieved by introducing the gene. Specifically, the effective induction of the differentiation of stem cells such as ES cells or iPS cells into hepatocytes can be achieved by introducing at least one gene selected from HEX gene, HNF4A gene, HNF6 gene and SOX17 gene into the stem cells.
    Type: Application
    Filed: October 22, 2010
    Publication date: September 13, 2012
    Applicant: JAPAN HEALTH SCIENCES FOUNDATION
    Inventors: Hiroyuki Mizuguchi, Kenji Kawabata, Mitsuru Inamura, Miho Furue
  • Patent number: 8198665
    Abstract: A semiconductor storage device includes: a substrate having a semiconductor layer at least on a surface thereof; and a plurality of quantum dot elements forming a charge storage layer formed above the semiconductor layer via a first insulating film that becomes a tunnel insulating film in such a manner that the quantum dot elements are connected with a bit line in series, wherein each quantum dot element forms a single electron memory.
    Type: Grant
    Filed: October 3, 2008
    Date of Patent: June 12, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Kawabata, Hisataka Meguro
  • Patent number: 8062939
    Abstract: A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor layer so as to sandwich the quantum dot therebetween; and a control electrode formed on the quantum dot through a second insulating film.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: November 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Kawabata
  • Publication number: 20110143503
    Abstract: A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor layer so as to sandwich the quantum dot therebetween; and a control electrode formed on the quantum dot through a second insulating film.
    Type: Application
    Filed: February 18, 2011
    Publication date: June 16, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kenji Kawabata
  • Patent number: 7910977
    Abstract: A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor layer so as to sandwich the quantum dot therebetween; and a control electrode formed on the quantum dot through a second insulating film.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: March 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Kawabata
  • Publication number: 20100214840
    Abstract: A multi-dot flash memory includes active areas arranged in a first direction, which extend to a second direction crossed to the first direction, the first and second direction being parallel to a surface of a semiconductor substrate, floating gates arranged in the first direction, which are provided above the active areas, a word line provided above the floating gates, which extends to the first direction, and bit lines provided between the floating gates, which extend to the second direction. Each of the floating gates has two side surfaces in the first direction, shapes of the two side surfaces are different from each other, and shapes of the facing surfaces of the floating gates which are adjacent to each other in the first direction are symmetrical.
    Type: Application
    Filed: September 21, 2009
    Publication date: August 26, 2010
    Inventors: Takashi Ichikawa, Hiroshi Watanabe, Kenji Kawabata