Patents by Inventor Kenji Maeguchi

Kenji Maeguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5061983
    Abstract: A method for manufacturing a semiconductor device that includes p- and n-type regions formed on an insulating substrate, and an interconnection layer electrically coupled with these p- and n-type regions. The interconnection layer is an n-type polycrystalline silicon layer which is electrically coupled with the p- and n-type regions through a metal silicide film formed between the interconnection layer and the p- and n-type regions.
    Type: Grant
    Filed: February 28, 1989
    Date of Patent: October 29, 1991
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hideharu Egawa, Yoshio Nishi, Kenji Maeguchi
  • Patent number: 4619037
    Abstract: A method of manufacturing a semiconductor device is disclosed. In the manufacturing method, an impurity diffusion layer as a first interconnection layer is formed on a semiconductor substrate. Then, an aluminum layer as a second interconnection layer is formed on the semiconductor substrate with an insulating film interposing therebetween. Another insulating layer is further formed on the aluminum layer. An anisotropic etching process is applied to the insulating layer, the second interconnection layer, and the insulating film, thereby forming a contact extending up to the first interconnection layer through these layers, and the insulating film. After the formation of the contact hole, an aluminum layer is formed on the entire surface of the insulating film including the inner surface of the contact hole. The aluminum layer formed in the contact hole electrically interconnects the first and second interconnecting layers.
    Type: Grant
    Filed: November 19, 1985
    Date of Patent: October 28, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Taguchi, Homare Matsumura, Kenji Maeguchi
  • Patent number: 4564583
    Abstract: Disclosed is a method for manufacturing a semiconductor device which comprises a process for forming a positive-type resist film and a negative-type resist film on a semiconductor substrate, a process for exposing predetermined regions of both resist films to radiation, a process for developing the upper resist film to form a first resist pattern adapted to be used as a mask for ion-implantation, a process for developing the lower resist film to form a second resist pattern opposite to the first resist pattern after peeling off the first resist pattern, and a process for treatment the semiconductor substrate using the second resist pattern as a mask.
    Type: Grant
    Filed: February 1, 1984
    Date of Patent: January 14, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Kenji Maeguchi
  • Patent number: 4498224
    Abstract: A method for manufacturing MOSFET type semiconductor devices comprises forming a gate insulation layer and a gate electrode on a single crystal semiconductor substrate; introducing impurities in the substrate using the gate electrode as a mask; introducing accelerated ions deeper into the substrate than the impurities and overlapping at least a portion of the region in which the impurities are introduced in order to convert that portion to an amorphous state; diffusing the impurities into the amorphous region using a heating atmosphere, in order to form source and drain regions and, at the same time, converting the amorphous region to a single crystal; and forming source and drain electrodes in contact with the source and drain regions.
    Type: Grant
    Filed: October 24, 1982
    Date of Patent: February 12, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Kenji Maeguchi
  • Patent number: 4491856
    Abstract: A semiconductor device includes p- and n-type semiconductor layers formed on an insulating substrate and an n-type interconnection layer formed to be electrically coupled with said n-type semiconductor layer. The n-type interconnection layer is formed in contact with the p-type semiconductor layer and is set at such a potential as to apply a reverse voltage across the p-n junction between the n-type interconnection layer and p-type semiconductor layer, so as to electrically isolate the n-type interconnection layer from the p-type semiconductor layer.
    Type: Grant
    Filed: February 27, 1984
    Date of Patent: January 1, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Hideharu Egawa, Yoshio Nishi, Kenji Maeguchi
  • Patent number: 4463492
    Abstract: A method for manufacturing a semiconductor device of a type in which a semiconductor element is formed on an insulating substrate. After ions which break the regularity of the crystal lattice of a monocrystalline semiconductor layer formed on the insulating substrate are implanted to form an amorphous semiconductor layer in part of the monocrystalline semiconductor layer, and after an impurity is doped in the semiconductor layer, a single annealing process is performed to recrystallize the amorphous semiconductor layer and at the same time to activate the doped impurity.
    Type: Grant
    Filed: September 24, 1982
    Date of Patent: August 7, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Kenji Maeguchi
  • Patent number: 4447823
    Abstract: A semiconductor device having silicon-on-sapphire structure in which a pn junction element is formed in a silicon substrate disposed on a sapphire plate. An oxide layer is formed in the surface area of the p-type region which serves to form the pn junction elements.
    Type: Grant
    Filed: March 5, 1981
    Date of Patent: May 8, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kenji Maeguchi, Hiroyuki Tango
  • Patent number: 4395726
    Abstract: A semiconductor device has a plurality of field effect transistors on an insulating substrate. A semiconductor film constituting at least one of the plurality of field effect transistors is thinner than a semiconductor film of the other field effect transistor or transistors.
    Type: Grant
    Filed: March 27, 1980
    Date of Patent: July 26, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Kenji Maeguchi