Patents by Inventor Kenji Masumoto

Kenji Masumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030062613
    Abstract: A type of semiconductor device and its manufacturing method, which can further miniaturize semiconductor devices and reduce design restrictions by minimizing the fillet around the semiconductor chip. The semiconductor package is constituted by fixing semiconductor chip 100 on insulating substrate 102 via die paste 104. Semiconductor chip 100 has top surface 112, where an electronic circuit is formed, and a bottom surface 114 adhered to insulating substrate 102. The bottom surface 114 is formed smaller than top surface 112. By forming bottom surface 114 smaller than top surface 112, the amount of the fillet spread out around semiconductor chip 100 can be reduced.
    Type: Application
    Filed: September 12, 2002
    Publication date: April 3, 2003
    Inventors: Kenji Masumoto, Mutsumi Masumoto
  • Patent number: 6525424
    Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.
    Type: Grant
    Filed: April 4, 2001
    Date of Patent: February 25, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Kensho Murata, Mutsumi Masumoto, Kenji Masumoto
  • Publication number: 20030036219
    Abstract: A method to realize low-profile semiconductor devices by grinding a resin sealed block and realize level grinding by eliminating warpage of the resin sealed block. Semiconductor devices 10 are produced by step (B) in which multiple semiconductor chips 11 are mounted face down onto the surface of substrate 12, step (C) in which molding resin 13 is injected onto substrate 12 in order to form resin sealed block 18 in which multiple semiconductor chips 11 are sealed, step (E) in which resin sealed block 18 is cut halfway from the side of substrate 12, and step (F) in which resin sealed block 18 is ground from the side of molding resin 13 in order to separate it into individual semiconductor devices 10.
    Type: Application
    Filed: August 13, 2002
    Publication date: February 20, 2003
    Inventors: Mutsumi Masumoto, Kenji Masumoto
  • Publication number: 20030036257
    Abstract: A method to realize extremely low profiling of semiconductor devices without reducing the yield and productivity. Semiconductor devices 10 are fabricated using step (B), in which multiple semiconductor chips 11 are mounted on substrate 12 having multiple adjoining chip mounting areas with their functional planes 11a facing the plane of said substrate; step (C), in which molding resin 13 is supplied to aforementioned substrate 12 in order to seal aforementioned multiple semiconductor chips 11; step (D), in which aforementioned molding resin 13 on aforementioned substrate 12 is ground together with said semiconductor chips 11 from its front side until aforementioned semiconductor chips 11 reaches a prescribed thickness; and step (F), in which substrate 12 mounted with aforementioned semiconductor chips 11 is cut into dice together with aforementioned molding resin 13 to form individual semiconductor devices 10.
    Type: Application
    Filed: August 9, 2002
    Publication date: February 20, 2003
    Inventors: Mutsumi Masumoto, Kenji Masumoto
  • Publication number: 20030017653
    Abstract: The problem of the present invention is to provide an insulation film capable of highly universal use for the production of semiconductor packages of different sizes and shapes.
    Type: Application
    Filed: July 19, 2001
    Publication date: January 23, 2003
    Inventors: Makoto Yoshino, Kenji Masumoto
  • Patent number: 6482730
    Abstract: A method to improve the resin sealing reliability in the manufacturing of a wafer-level CSP. The method for manufacturing a semiconductor device of the present invention includes a process that forms wiring 14 and conductive supports 16, which electrically connect electrode pads 10a and corresponding external terminals, on a wafer 10 on which semiconductor elements are formed. In subsequent processes, a groove 18 (preferably V shaped) is formed in the surface of the above-mentioned wafer along the boundary lines of the respective semiconductor elements. Next, the end surfaces of the above-mentioned conductive supports 16 are exposed, and the above-mentioned wafer surface is covered with a resin 19 so that external terminals 20 are arranged on the end surfaces of the conductive supports. In the final process, along the boundary lines of the above-mentioned semiconductor elements, packaged semiconductor devices 32 are obtained by dicing the above-mentioned wafer.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: November 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Mutsumi Masumoto, Kenji Masumoto
  • Publication number: 20020145198
    Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.
    Type: Application
    Filed: April 4, 2001
    Publication date: October 10, 2002
    Inventors: Kensho Murata, Mutsumi Masumoto, Kenji Masumoto
  • Publication number: 20020050653
    Abstract: In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is mounted on isolated substrate 12. Multiple stud bumps are stacked on top of the pads 20a which are located on the inner rows, and these stud bumps comprise stud bump stack 28. Conductive wire 22 connects the lands 18 on the isolated substrate with the corresponding bonding pads 20. The wire is formed with its beginning at the land and its end at the bonding pad. Via the stud bump stacks 28, the ends of conductive wire 22a on the inner pads are in a higher position than the ends of conductive wires 22b on the outer pads, so that the problem of neighboring conductive wires coming into contact does not occur.
    Type: Application
    Filed: July 19, 2001
    Publication date: May 2, 2002
    Inventors: Kenji Masumoto, Mutsumi Masumoto, Akira Karashima
  • Patent number: 6269999
    Abstract: A semiconductor chip mounting method to prevent the occurrence of particles created while mounting the semiconductor chip onto a substrate using ultrasonic thermocompression bonding. The mounting method of the present invention utilizing ultrasonic vibrations involves the following steps: a semiconductor chip having conductive bumps on its main surface is held by its back via an elastic film using a suction tool having a suction hole, the semiconductor chip is positioned against a substrate provided with connection wires corresponding to said conductive bumps, and the semiconductor chip is mounted onto the substrate in such a manner that the conductive bumps connect to said connection wires, and ultrasonic vibrations are applied from the suction tool to the semiconductor chip via said film while said semiconductor chip is being pressed against said substrate in order to bond said conductive bumps with said connection wires.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: August 7, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Tomohiro Okazaki, Kenji Masumoto, Mutsumi Masumoto, Katsumi Yamaguchi
  • Patent number: 5258331
    Abstract: A method for manufacturing a semiconductor device, which has the steps of connecting adjacent outer leads, with an insulating photoresist or prepeg material with a width locally provided only in areas with said width along the direction of arrangement of outer leads, and of resin-sealing areas other than said outer leads and said insulating material while preventing the outflow of sealing resin by way of said insulating photoresist or prepeg material.
    Type: Grant
    Filed: March 16, 1992
    Date of Patent: November 2, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Kenji Masumoto, Takashi Nakashima
  • Patent number: 5176366
    Abstract: A semiconductor device in which outer leads adjoining in the direction of arrangement of said outer leads are connected by an insulating material with a predetermined width, locally provided only in the areas with said predetermined width along said direction of arrangement, and in which areas other than said outer leads and said insulating material are resin-sealed. A method for manufacturing a semiconductor device, which has the steps of connecting adjacent outer leads, with an insulating material with a predetermined width locally provided only in areas with said predetermined width along the direction of arrangement of outer leads, and of resin-sealing areas other than said outer leads and said insulating material while preventing the outflow of sealing resin by way of said insulating material.
    Type: Grant
    Filed: October 4, 1990
    Date of Patent: January 5, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Kenji Masumoto, Takashi Nakashima