Patents by Inventor Kenji Takakura

Kenji Takakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200377833
    Abstract: A cell picking device includes a sucker having a pipette tip attached to a tip portion of the sucker and is used to suck the cell from a tip of the pipette tip, a driver configured to cause the sucker to perform a suction operation and move the sucker in a horizontal-plane direction and an axial direction of the pipette tip with the sucker inclined with respect to a vertical direction. A controller moves the sucker such that the tip of the pipette tip moves in a horizontal direction while being in contact with a bottom surface of the container installed on the sample mounting stage in a predetermined position on the sample mounting stage to desorb a cell arranged in the predetermined position from the bottom surface of the container, and suck the cell desorbed from the bottom surface of the container from the tip of the pipette tip.
    Type: Application
    Filed: March 16, 2018
    Publication date: December 3, 2020
    Inventors: Takashi INOUE, Kenji TAKAKURA, Yoshitaka NODA, Yasuaki MATSUNAGA, Mika OKADA, Akari TAKEDA
  • Patent number: 10372033
    Abstract: The present invention provides an imprint apparatus comprising a plurality of processing devices configured to perform imprint processes for a plurality of substrates in parallel, and a controller configured to control the plurality of processing devices, wherein the controller is configured to control the plurality of processing devices so that each of the plurality of processing devices performs imprint processes for a plurality of regions whose positions correspond to each other over the plurality of substrates, and so that the plurality of processing devices respectively perform imprint processes for a plurality of regions whose positions are different from each other and which have shapes corresponding to each other in a single substrate.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: August 6, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kenji Yamamoto, Noburu Takakura
  • Publication number: 20110089525
    Abstract: A trench is formed on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; a second insulation film is embedded in the trench and flattened; an upper portion of the first insulation film is selectively removed, and a part of a side face of the second insulation film is exposed; a part of the second insulation film is isotropically removed; a lower portion of the remaining first insulation film is selectively removed; and then a part of the remaining second insulation film is further isotropically removed so that an upper face of the second insulation film is at a predetermined height from a surface of the semiconductor substrate, a taper having a minimum taper angle of 90° or more is formed on the side face of the second insulation film, and a STI is formed.
    Type: Application
    Filed: December 16, 2010
    Publication date: April 21, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Ito, Kunihiro Miyazaki, Kenji Takakura
  • Patent number: 7875527
    Abstract: A trench is formed on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; a second insulation film is embedded in the trench and flattened; an upper portion of the first insulation film is selectively removed, and a part of a side face of the second insulation film is exposed; a part of the second insulation film is isotropically removed; a lower portion of the remaining first insulation film is selectively removed; and then a part of the remaining second insulation film is further isotropically removed so that an upper face of the second insulation film is at a predetermined height from a surface of the semiconductor substrate, a taper having a minimum taper angle of 90° or more is formed on the side face of the second insulation film, and a STI is formed.
    Type: Grant
    Filed: January 26, 2009
    Date of Patent: January 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Ito, Kunihiro Miyazaki, Kenji Takakura
  • Publication number: 20090212387
    Abstract: A trench is formed on a semiconductor substrate with a first insulation film patterned on the semiconductor substrate as a mask; a second insulation film is embedded in the trench and flattened; an upper portion of the first insulation film is selectively removed, and a part of a side face of the second insulation film is exposed; a part of the second insulation film is isotropically removed; a lower portion of the remaining first insulation film is selectively removed; and then a part of the remaining second insulation film is further isotropically removed so that an upper face of the second insulation film is at a predetermined height from a surface of the semiconductor substrate, a taper having a minimum taper angle of 90° or more is formed on the side face of the second insulation film, and a STI is formed.
    Type: Application
    Filed: January 26, 2009
    Publication date: August 27, 2009
    Inventors: Yasuhiro Ito, Kunihiro Miyazaki, Kenji Takakura
  • Patent number: 5686830
    Abstract: A method of supplying positive temperature coefficient thermistor elements in which a plurality of positive temperature coefficient thermistor elements 1 are divided into groups G.sub.1 to G.sub.8 for each range of predetermined resistance values, two arbitrary positive temperature coefficient thermistor elements are taken out of one of the groups G.sub.1 to G.sub.8 and supplied as one set of positive temperature coefficient thermistor elements.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: November 11, 1997
    Assignee: Muarata Manufacturing Co., Ltd.
    Inventors: Kenji Takakura, Yuichi Takaoka
  • Patent number: 5425099
    Abstract: A positive temperature coefficient thermistor element comprising a plate-shaped ceramic body made of a ceramic material whose Curie temperature is in the range of 60.degree. to 120.degree. C., and having a thickness of 2.5 to 5.0 mm, and electrodes formed on both major surfaces of the ceramic body.
    Type: Grant
    Filed: April 6, 1994
    Date of Patent: June 13, 1995
    Assignee: Murata Mfg. Co., Ltd.
    Inventors: Kenji Takakura, Katsuyuki Uchida
  • Patent number: 5315652
    Abstract: A terminal for telegraph and telephone systems using as an overvoltage/overcurrent protecting component a positive temperature coefficient thermistor element comprising a plate-shaped ceramic body made of a ceramic material whose Curie temperature is in the range of 60.degree. to 120.degree. C., and having a thickness of 2.5 to 5.0 mm, and electrodes formed on both major surfaces of the ceramic body.
    Type: Grant
    Filed: March 11, 1992
    Date of Patent: May 24, 1994
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Takakura, Katsuyuki Uchida