Patents by Inventor Kenjiro Uesugi
Kenjiro Uesugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230100683Abstract: A nitride semiconductor substrate (11, 21) includes: a substrate (2); and an AlN-containing film (100, 200) provided above the substrate (2). A thickness of the AlN-containing film (100, 200) is at most 10000 nm, and a threading dislocation density of the AlN-containing film (100, 200) is at most 2×108 cm?2.Type: ApplicationFiled: February 26, 2021Publication date: March 30, 2023Applicant: MIE UNIVERSITYInventors: Hideto MIYAKE, Ding WANG, Kenjiro UESUGI
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Patent number: 11024717Abstract: In one embodiment, a semiconductor device is provided with a substrate, a first nitride semiconductor layer above the substrate, a second nitride semiconductor layer which is provided on the first nitride semiconductor layer and is in contact with the first nitride semiconductor layer, a source electrode provided between the substrate and the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a drain electrode provided on the second nitride semiconductor layer and electrically connected to the second nitride semiconductor layer, a gate insulating layer provided at least between the substrate and the first nitride semiconductor layer, a gate electrode between the substrate and the gate insulating layer, and a first insulating layer between the substrate and the gate insulating layer to cover the gate electrode and the source electrode.Type: GrantFiled: August 31, 2018Date of Patent: June 1, 2021Assignee: Kabushiki Kaisha ToshibaInventors: Jumpei Tajima, Toshiki Hikosaka, Kenjiro Uesugi, Masahiko Kuraguchi, Shinya Nunoue
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Patent number: 10629724Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first, second, third, and fourth semiconductor regions, and an insulating portion. The first electrode includes first and second electrode portions. The first semiconductor region includes first, second, and third semiconductor portions. The first semiconductor portion is provided between the first electrode portion and the second electrode. The second semiconductor portion is provided between the second electrode portion and the third electrode. The third semiconductor portion is provided between the first and second semiconductor portions. The second semiconductor region is provided between the first semiconductor portion and the second electrode. The third semiconductor region is positioned between the second semiconductor region and the third electrode. The insulating portion includes first and second insulating regions.Type: GrantFiled: February 21, 2018Date of Patent: April 21, 2020Assignee: Kabushiki Kaisha ToshibaInventors: Kenjiro Uesugi, Shigeya Kimura, Masahiko Kuraguchi
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Patent number: 10483354Abstract: In one embodiment, a nitride semiconductor device is provided with a first semiconductor layer that is a layer of Alx1Ga(1-x1)N (0<x1?1), a second semiconductor layer that is on the first semiconductor layer and is a layer of a nitride semiconductor Iny2Alx2Ga(1-x2-y2)N (0<x2<1, 0<y2<1, 0<x2+y2?1) containing indium, a third semiconductor layer that is on the second semiconductor layer and is a layer of Alx3Ga(1-x3)N (0?x3<1), and a fourth semiconductor layer that is on the third semiconductor layer and is an layer of Iny4Alx4Ga(1-x4-y4)N (0<x4<1, 0?y4<1, 0<x4+y4?1).Type: GrantFiled: August 31, 2018Date of Patent: November 19, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Kenjiro Uesugi, Shigeya Kimura, Toshiki Hikosaka
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Patent number: 10475915Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating layer. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes at least one of Alx1Ga1-x1N (0<x1<1) or p-type Alz1Ga1-z1N (0?z1<1) and has a first surface, a second surface, and a third surface. The second layer includes Alx2Ga1-x2N (0?x2<1 and x2<x1) and includes a first partial region, a second partial region, and a third partial region. The third layer includes Alx3Ga1-x3N (0<x3<1 and x2<x3) and includes a fourth partial region, a fifth partial region, and a sixth partial region.Type: GrantFiled: March 20, 2019Date of Patent: November 12, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Jumpei Tajima, Toshiki Hikosaka, Kenjiro Uesugi, Shigeya Kimura, Masahiko Kuraguchi, Shinya Nunoue
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Publication number: 20190296111Abstract: In one embodiment, a semiconductor device is provided with a substrate, a first nitride semiconductor layer above the substrate, a second nitride semiconductor layer which is provided on the first nitride semiconductor layer and is in contact with the first nitride semiconductor layer, a source electrode provided between the substrate and the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a drain electrode provided on the second nitride semiconductor layer and electrically connected to the second nitride semiconductor layer, a gate insulating layer provided at least between the substrate and the first nitride semiconductor layer, a gate electrode between the substrate and the gate insulating layer, and a first insulating layer between the substrate and the gate insulating layer to cover the gate electrode and the source electrode.Type: ApplicationFiled: August 31, 2018Publication date: September 26, 2019Applicant: Kabushiki Kaisha ToshibaInventors: Jumpei Tajima, Toshiki Hikosaka, Kenjiro Uesugi, Masahiko Kuraguchi, Shinya Nunoue
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Patent number: 10395932Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, and first, second, third, fourth, and fifth semiconductor regions. The first electrode includes a first conductive region. The second electrode includes a second conductive region separated. The third electrode includes a third conductive region. The first semiconductor region is separated from the first, second, and third conductive regions. The second semiconductor region is provided between the first conductive and semiconductor regions, between the second conductive and first semiconductor regions, and between the third conductive and first semiconductor regions. The third semiconductor region is provided between the first conductive region and the second semiconductor region. The fourth semiconductor region is provided between the second conductive region and the second semiconductor region.Type: GrantFiled: August 7, 2017Date of Patent: August 27, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Kenjiro Uesugi, Toshiki Hikosaka, Shinya Nunoue
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Publication number: 20190237550Abstract: In one embodiment, a nitride semiconductor device is provided with a first semiconductor layer that is a layer of Alx1Ga(1-x1)N (0<x1?1), a second semiconductor layer that is on the first semiconductor layer and is a layer of a nitride semiconductor Iny2Alx2Ga(1-x2-y2)N (0<x2<1, 0<y2<1, 0<x2+y2?1) containing indium, a third semiconductor layer that is on the second semiconductor layer and is a layer of Alx3Ga(1-x3)N (0?x3<1), and a fourth semiconductor layer that is on the third semiconductor layer and is an layer of Iny4Alx4Ga(1-x4-y4)N (0<x4<1, 0?y4<1, 0<x4+y4?1).Type: ApplicationFiled: August 31, 2018Publication date: August 1, 2019Applicant: Kabushiki Kaisha ToshibaInventors: Kenjiro Uesugi, Shigeya Kimura, Toshiki Hikosaka
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Patent number: 10355119Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include forming a trench and exposing a portion of a first film at a bottom portion of the trench by removing a portion of a second film by performing dry etching using a gas including a first element. The second film is provided on the first film. The first film includes Alx1Ga1-x1N (0?x1<1). The second film includes Alx2Ga1-x2N (0<x2<1 and x1<x2). The method can include performing heat treatment while causing the portion being exposed of the first film to contact an atmosphere including NH3, forming an insulating film on the portion of the first film after the heat treatment, and forming an electrode on the insulating film.Type: GrantFiled: August 7, 2017Date of Patent: July 16, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Kenjiro Uesugi, Aya Shindome, Daimotsu Kato, Masahiko Kuraguchi, Shinya Nunoue
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Publication number: 20190214495Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating layer. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes at least one of Alx1Ga1-x1N (0<x1<1) or p-type Alz1Ga1-z1N (0?z1<1) and has a first surface, a second surface, and a third surface. The second layer includes Alx2Ga1-x2N (0?x2<1 and x2<x1) and includes a first partial region, a second partial region, and a third partial region. The third layer includes Alx3Ga1-x3N (0<x3<1 and x2<x3) and includes a fourth partial region, a fifth partial region, and a sixth partial region.Type: ApplicationFiled: March 20, 2019Publication date: July 11, 2019Applicant: Kabushiki Kaisha ToshibaInventors: Jumpei TAJIMA, Toshiki HIKOSAKA, Kenjiro UESUGI, Shigeya KIMURA, Masahiko KURAGUCHI, Shinya NUNOUE
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Patent number: 10283633Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating layer. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes at least one of Alx1Ga1-x1N (0<x1<1) or p-type Alz1Ga1-z1N (0?z1<1) and has a first surface, a second surface, and a third surface. The second layer includes Alx2Ga1-x2N (0?x2<1 and x2<x1) and includes a first partial region, a second partial region, and a third partial region. The third layer includes Alx3Ga1-x3N (0<x3<1 and x2<x3) and includes a fourth partial region, a fifth partial region, and a sixth partial region.Type: GrantFiled: February 20, 2018Date of Patent: May 7, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Jumpei Tajima, Toshiki Hikosaka, Kenjiro Uesugi, Shigeya Kimura, Masahiko Kuraguchi, Shinya Nunoue
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Publication number: 20190088770Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating layer. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes at least one of Alx1Ga1-x1N (0<x1<1) or p-type Alz1Ga1-z1N (0?z1<1) and has a first surface, a second surface, and a third surface. The second layer includes Alx2Ga1-x2N (0?x2<1 and x2<x1) and includes a first partial region, a second partial region, and a third partial region. The third layer includes Alx3Ga1-x3N (0<x3<1 and x2<x3) and includes a fourth partial region, a fifth partial region, and a sixth partial region.Type: ApplicationFiled: February 20, 2018Publication date: March 21, 2019Applicant: Kabushiki Kaisha ToshibaInventors: Jumpei TAJIMA, Toshiki HIKOSAKA, Kenjiro UESUGI, Shigeya KIMURA, Masahiko KURAGUCHI, Shinya NUNOUE
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Patent number: 10186588Abstract: According to one embodiment, a semiconductor substrate includes a first semiconductor layer including Alx1Ga1-x1N (0<x1?1) and including carbon and oxygen, and a second semiconductor layer including Alx2Ga1-x2N (0<x2<x1) and including carbon and oxygen. A second ratio of a carbon concentration of the second semiconductor layer to an oxygen concentration of the second semiconductor layer is 730 or more.Type: GrantFiled: February 20, 2018Date of Patent: January 22, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Daimotsu Kato, Hisashi Yoshida, Jumpei Tajima, Kenjiro Uesugi, Toshiki Hikosaka, Miki Yumoto, Shinya Nunoue, Masahiko Kuraguchi
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Publication number: 20180358462Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first, second, third, and fourth semiconductor regions, and an insulating portion. The first electrode includes first and second electrode portions. The first semiconductor region includes first, second, and third semiconductor portions. The first semiconductor portion is provided between the first electrode portion and the second electrode. The second semiconductor portion is provided between the second electrode portion and the third electrode. The third semiconductor portion is provided between the first and second semiconductor portions. The second semiconductor region is provided between the first semiconductor portion and the second electrode. The third semiconductor region is positioned between the second semiconductor region and the third electrode. The insulating portion includes first and second insulating regions.Type: ApplicationFiled: February 21, 2018Publication date: December 13, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Kenjiro UESUGI, Shigeya Kimura, Masahiko Kuraguchi
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Publication number: 20180219088Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include forming a trench and exposing a portion of a first film at a bottom portion of the trench by removing a portion of a second film by performing dry etching using a gas including a first element. The second film is provided on the first film. The first film includes Alx1Ga1-x1N (0?x1<1). The second film includes Alx2Ga1-x2N (0<x2<1 and x1<x2). The method can include performing heat treatment while causing the portion being exposed of the first film to contact an atmosphere including NH3, forming an insulating film on the portion of the first film after the heat treatment, and forming an electrode on the insulating film.Type: ApplicationFiled: August 7, 2017Publication date: August 2, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Kenjiro UESUGI, Aya SHINDOME, Daimotsu KATO, Masahiko KURAGUCHI, Shinya NUNOUE
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Publication number: 20180174849Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, and first, second, third, fourth, and fifth semiconductor regions. The first electrode includes a first conductive region. The second electrode includes a second conductive region separated. The third electrode includes a third conductive region. The first semiconductor region is separated from the first, second, and third conductive regions. The second semiconductor region is provided between the first conductive and semiconductor regions, between the second conductive and first semiconductor regions, and between the third conductive and first semiconductor regions. The third semiconductor region is provided between the first conductive region and the second semiconductor region. The fourth semiconductor region is provided between the second conductive region and the second semiconductor region.Type: ApplicationFiled: August 7, 2017Publication date: June 21, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Kenjiro UESUGI, Toshiki HIKOSAKA, Shinya NUNOUE
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Patent number: 9972657Abstract: According to one embodiment, a semiconductor light emitting element (110) includes a metal layer (40), a first to a fourth semiconductor layers (10a, 20a, 10b, 20b), a first and a second light emitting layers (30a, 30b), a first to a sixth electrodes (e1-e6), and a first inter-element interconnect section (12). The first semiconductor layer (10a) includes a first to a third regions (r1-r3). The second semiconductor layer (20a) is provided between the first region (r1) and the metal layer (40) and between the second region (r2) and the metal layer (40). The third semiconductor layer (10b) includes a fourth to a sixth regions (r4-r6). The fourth semiconductor layer (20b) is provided between the fourth region (r4) and the metal layer (40) and between the fifth region (r5) and the metal layer (40). The first inter-element interconnect section (12) is provided between the second electrode (e2) and the metal layer (40) and between the sixth electrode (e6) and the metal layer (40).Type: GrantFiled: July 28, 2015Date of Patent: May 15, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Jumpei Tajima, Hiroshi Ono, Toshihide Ito, Kenjiro Uesugi, Shinya Nunoue
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Publication number: 20170221962Abstract: According to one embodiment, a semiconductor light emitting element (110) includes a metal layer (40), a first to a fourth semiconductor layers (10a, 20a, 10b, 20b), a first and a second light emitting layers (30a, 30b), a first to a sixth electrodes (e1-e6), and a first inter-element interconnect section (12). The first semiconductor layer (10a) includes a first to a third regions (r1-r3). The second semiconductor layer (20a) is provided between the first region (r1) and the metal layer (40) and between the second region (r2) and the metal layer (40). The third semiconductor layer (10b) includes a fourth to a sixth regions (r4-r6). The fourth semiconductor layer (20b) is provided between the fourth region (r4) and the metal layer (40) and between the fifth region (r5) and the metal layer (40). The first inter-element interconnect section (12) is provided between the second electrode (e2) and the metal layer (40) and between the sixth electrode (e6) and the metal layer (40).Type: ApplicationFiled: July 28, 2015Publication date: August 3, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Jumpei TAJIMA, Hiroshi ONO, Toshihide ITO, Kenjiro UESUGI, Shinya NUNOUE
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Patent number: 9590009Abstract: A semiconductor light emitting element includes a base body, a first semiconductor layer, a second semiconductor layer, a first light emitting layer, a first conductive layer, a third semiconductor layer, a fourth semiconductor layer, a second light emitting layer, a second conductive layer, a first member, and a second member. The first member includes a first end portion and a second end portion. The first end portion is positioned between the base body and the first conductive layer and electrically connected to the first conductive layer, the second end portion not overlapping the second conductive layer. The second member includes a third end portion and a fourth end portion. The third end portion is positioned between the base body and the second conductive layer and electrically connected to the second conductive layer. The fourth end portion is electrically connected to the second end portion.Type: GrantFiled: August 11, 2015Date of Patent: March 7, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Jumpei Tajima, Hiroshi Ono, Toshihide Ito, Kenjiro Uesugi, Shinya Nunoue
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Publication number: 20170025578Abstract: According to one embodiment, a nitride semiconductor element includes a p-type semiconductor layer and a p-side electrode. The p-type semiconductor layer includes a nitride semiconductor, and has a first surface. The p-side electrode contacts the first surface. The first surface is a semi-polar plane. The first surface includes a plurality of protrusions. A height of the protrusions along a first direction is not less than 1 nanometer and not more than 5 nanometers. The first direction is from the p-type semiconductor layer toward the p-side electrode. A density of the protrusions in the first surface is more than 1.0×1010/cm2 and not more than 6.1×1010/cm2.Type: ApplicationFiled: February 25, 2016Publication date: January 26, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Toshiki HIKOSAKA, Hisashi Yoshida, Kenjiro Uesugi, Hiroshi Ono, Shinya Nunoue