Abstract: A method and apparatus for a self-checking multi-threaded processor includes a first thread for generating a first I/O request; a second thread for generating a second I/O request; and a self-checking component for comparing the first I/O request and second I/O request. Processor operation is selectively suspended based on the comparison of the first I/O request and the second I/O request. The self-checking multi-threaded processor may include a third thread for generating a third I/O request; the self-checking component may compare the I/O requests of the first thread, the second thread, and the third thread; and processor operation may selectively continue with issuance if at least two the first I/O request, the second I/O request, and the third I/O request match. The second thread may begin processing to generate the second I/O request upon the generation of the first I/O request by the first thread.

Abstract: An apparatus and method are disclosed that define a new, uniform I/O (input/output) interface architecture between the processor module and the motherboard of a computer system, and between the motherboard and expansion boards, via uniform connectors designed to work with the new architecture, such that many different pin-outs are available to the processor module, the interface being dynamically configurable by component control logic of the processor module. Positioning of supplemental connectors (e.g. for I/O or communications) on edges of the cards defines an unimpeded airflow path allowing for efficient cooling of the system.

Abstract: A semiconductor device, such as a multiprocessor chip for a computer system, includes a total number of on-board components which is greater than the number of that component required by the system. The chip may be provided with multiple I/O controllers, e.g. more than one controller per I/O interface, and the I/O controllers can act as backups to one another, with failover logic controlling the backup process. In addition, the number of processors formed on the chip may be greater than the number required by the system, allowing multiple levels of redundancy and greater successful manufacturing yields.

Abstract: A method and apparatus for a self-checking multi-threaded processor includes a first thread for generating a first I/O request; a second thread for generating a second I/O request; and a self-checking component for comparing the first I/O request and second I/O request. Processor operation is selectively suspended based on the comparison of the first I/O request and the second I/O request. The self-checking multi-threaded processor may include a third thread for generating a third I/O request; the self-checking component may compare the I/O requests of the first thread, the second thread, and the third thread; and processor operation may selectively continue with issuance if at least two the first I/O request, the second I/O request, and the third I/O request match. The second thread may begin processing to generate the second I/O request upon the generation of the first I/O request by the first thread.

Abstract: An apparatus and method are disclosed for switching the context of state elements of a very fast processor within a clock cycle when a cache miss occurs. To date, processors either stay idle or execute instructions out of order when they encounter cache misses. As the speed of processors become faster, the penalty for a cache miss is heavier. Having multiple copies of state elements on the processor and coupling them to a multiplexer permits the processor to save the context of the current instructions and resume executing new instructions within one clock cycle. The invention disclosed is particularly useful for minimizing the average instruction cycle time for a processor with a main memory access time exceeding 15 processor clock cycles. It is understood that the number of processes who's states are duplicated may easily be a large number n.

Abstract: A memory unit connected in a data processing system including a central processor unit and an input/output unit. The memory unit is connected to the central processor unit through one port, and to the input/output unit through a second port. When the central processor unit wants to transfer data with the input/output unit, it does so through the memory unit.

Abstract: A memory unit for connection in a data processing system in which the central processor unit may transfer data to or retrieve data from portions of two storage locations in one transfer. The memory unit has a data rotating and storage network that rotates the data and stores it as necessary for its transfer to or from the addressed storage locations.