Abstract: A VGA controller using address translation logic to drive a dual scan LCD panel is disclosed. The address translation logic converts the display data into an interleaved format in the display buffer, allowing the VGA controller to simultaneously access the display data for both LCD inputs without the need for a separate half-frame buffer memory. Elimination of this half-frame buffer memory reduces system cost with no reduction in performance of the VGA controller.

Abstract: An improved VGA Controller with Arbitration Logic and method therefor is provided to enhance system performance by efficiently using the minimum amount of bus bandwidth required. This Controller includes a bus to the Frame Buffer that either the system CPU or the Display Controller may access and control. The Display Controller includes a Display FIFO which stores display data from the Frame Buffer for the Display Controller to use. This Display FIFO coupled with the Arbitration Logic makes it possible for the Display Controller to continue to output display data even when the system CPU is accessing the display data in the Frame Buffer. The Arbitration Logic attempts to keep the Display FIFO as full as possible such that a bus request by the system CPU can be immediately granted when received.

Abstract: A device and method for converting 18-bit RGB data to 5-bit gray scale data is disclosed. This device and method comprises a barrel shifter, an adder, a palette storage register, and control logic. The red data is loaded first into the barrel shifter, and is shifted, added and stored in the palette storage register. The green data is then loaded into the barrel shifter and is shifted and added to the value stored in the palette storage register. The blue data is then loaded into the barrel shifter and is shifted and added to the value stored in the palette storage register, thereby completing the conversion. The five most significant bits of the six-bit palette storage register are output as gray scale data. The shifting and adding of these six-bit integers allow a binary approximation of the appropriate coefficients for each block of color data.

Abstract: A dual edge-triggered digital storage element is disclosed. This storage element operates much like a standard digital latch, with the exception that the data input is clocked to the output on both the rising and the falling edge of the clock input. This allows the frequency of the clock signal to be reduced by half, reducing system complexity and reducing power consumption.

Abstract: A circuit generates a system clock signal. On a first input of the circuit a first oscillating signal is placed. On a second input, a second oscillating signal may be placed. Clock sense logic is connected to the second input. The clock sense logic detects whether the second oscillation signal is present on the second input. When the second oscillating signal is not present on the second input, the first oscillating signal is selected to be used to generate the system clock. When the second oscillating signal is present on the second input, the second oscillating signal is selected to be used to generate the system clock. The selected oscillating signal is divided to produce the system clock signal. A first frequency divider divides the selected oscillating signal by a first amount. In parallel, a second frequency divider divides the selected oscillating signal by a second amount.