Patents by Inventor Kenneth P. Snowdon

Kenneth P. Snowdon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8542055
    Abstract: A circuit for selectively providing a signal from a source to a sink is provided. The circuit includes a field effect transistor having a conducting state and a non-conducting state, the field effect transistor having a gate, a source, and a drain. The circuit also includes a first comparator configured to provide a first output based on a difference between a source voltage at the source of the field effect transistor and a first reference voltage. Finally, the circuit includes a switching amplifier configured to apply a first gate voltage to the gate of the field effect transistor as a function of the first output of the first comparator.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: September 24, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Kenneth P. Snowdon
  • Publication number: 20130229225
    Abstract: In one general aspect, an apparatus can include a complementary switch circuit including a first portion and a second portion, and a first driver circuit coupled to the first portion of the complementary switch circuit. The apparatus can include a positive charge pump device coupled to the first driver, and a second driver circuit coupled to the second portion of the complementary switch circuit. The apparatus can also include a negative charge pump device coupled to the second driver circuit.
    Type: Application
    Filed: March 2, 2012
    Publication date: September 5, 2013
    Inventors: Nickole Gagne, Kenneth P. Snowdon
  • Patent number: 8525575
    Abstract: A system includes a pass switch circuit and a first pass switch activation circuit. The pass switch circuit includes an impedance circuit and a pass transistor having a first source/drain connection, a second source/drain connection, and a gate input. The pass switch circuit passes an electronic signal from the first source/drain connection to the second source/drain connection in response to activation of the gate input. An impedance transfer function of the pass switch circuit is determined at least in part by an impedance of the impedance circuit and the impedance is sized to minimize attenuation of the electronic signal due to the impedance transfer function of the pass switch circuit. The first pass switch activation circuit provides a first activation signal to the gate input in response to an enable signal.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: September 3, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Kenneth P. Snowdon
  • Publication number: 20130225067
    Abstract: In one general aspect, a repeater can include an input terminal configured to be coupled to a first portion of a MIPI signal path. The MIPI signal path being a unidirectional path between a receiver and a transmitter, the input terminal configured to receive a set of signals from the receiver via the MIPI signal path. The repeater can include an output terminal configured to be coupled to a second portion of the MIPI signal path, the first portion of the MIPI signal path and the second portion of the MIPI signal path having a combined distance greater than 30 centimeters.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Inventors: Robert A Card, Kenneth P. Snowdon
  • Publication number: 20130169255
    Abstract: This document discusses, among other things, apparatus and methods for providing a power-on-reset signal. An example apparatus can include a regulator configured to receive a supply voltage and to provide a regulated voltage at an output, and a power-on-reset (POR) circuit including a POR comparator. The POR circuit can be configured to provide an indication that the regulated voltage is below a threshold level using an output of the POR comparator and to disable the POR comparator when the regulated voltage is above the threshold level.
    Type: Application
    Filed: December 30, 2011
    Publication date: July 4, 2013
    Inventors: Tyler Daigle, Kenneth P. Snowdon, Nickole Gagne, Julie Lynn Stultz
  • Publication number: 20130162334
    Abstract: Generally, this disclosure provides negative charge pump circuitry that is configured to supply a voltage that is less than a reference voltage (such as ground). The charge pump circuitry includes blocking circuitry that reduces or eliminates charge leakage so that a negative voltage may be developed at the output. The charge pump circuitry generally includes complimentary pairs of MOS switches that switch in a complimentary fashion according to charge developed on complimentary capacitors to provide a negative voltage power supply.
    Type: Application
    Filed: December 27, 2011
    Publication date: June 27, 2013
    Inventor: Kenneth P. Snowdon
  • Publication number: 20130162356
    Abstract: In one general aspect, an apparatus can include a phase frequency detector configured to produce a plurality of indicators of relative differences between a frequency of a target oscillator signal and a frequency of a reference oscillator signal. The apparatus can also include a pulse generator configured to produce a plurality of pulses based on the plurality of indicators. The plurality of pulses can include a first portion configured to trigger an increase in the frequency of the target oscillator signal and the plurality of pulses including a second portion configured to trigger a decrease in the frequency of the target oscillator signal.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 27, 2013
    Inventors: Kenneth P. Snowdon, Jeffery S. Martin
  • Publication number: 20130154720
    Abstract: This document discusses, among other things, a signal switch circuit including a first field effect transistor (FET) configured to couple a first node to a second node in an on-state and a charge pump circuit configured to provide a first supply voltage to control the FET, wherein a reference voltage of the charge pump circuit is coupled to a well of the FET to maintain a constant gate to source voltage of the FET during the on-state.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 20, 2013
    Inventor: Kenneth P. Snowdon
  • Publication number: 20130154601
    Abstract: This document discusses, among other things, apparatus and methods for providing over-voltage transient protection of a voltage regulator. In an example, an apparatus can include a first transistor including a control node and first and second switch nodes, and a low-pass filter configured to couple to the control node of the first transistor and to switch the first transistor to a first state when a voltage change of the supply voltage exceeds a threshold. The first transistor, in the first state, can be configured to couple a control node of a second transistor to the supply voltage to protect components coupled to a regulator transistor.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 20, 2013
    Inventors: Kenneth P. Snowdon, Hrvoje Jasa
  • Patent number: 8456225
    Abstract: Generally, this disclosure provides negative charge pump circuitry that is configured to supply a voltage that is less than a reference voltage (such as ground). The charge pump circuitry includes blocking circuitry that reduces or eliminates charge leakage so that a negative voltage may be developed at the output. The charge pump circuitry generally includes complimentary pairs of MOS switches that switch in a complimentary fashion according to charge developed on complimentary capacitors to provide a negative voltage power supply.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: June 4, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Kenneth P. Snowdon
  • Publication number: 20120287538
    Abstract: An apparatus comprises an integrated circuit (IC) including an external IC connection, a high impedance circuit, a biasing circuit communicatively coupled to the external IC connection via the high impedance circuit, and an electro-static discharge (ESD) protection circuit coupled to the biasing circuit to form a circuit shunt path leading from the IC external connection to the ESD protection circuit via the high impedance circuit.
    Type: Application
    Filed: May 9, 2011
    Publication date: November 15, 2012
    Inventors: Christopher A. Bennett, Kenneth P. Snowdon
  • Publication number: 20120206845
    Abstract: This document discusses methods and apparatus for preventing or reducing sub-threshold pass gate leakage. In an example, an apparatus can include a pass gate configured to electrically couple a first node with a second node in a first state and to electrically isolate the first node from the second node in a second state, control logic configured to control the pass gate, wherein the control logic includes a supply rail, and an over-voltage circuit configured to compare voltages received at a plurality of input nodes and to couple an output to an input node a highest voltage. In an example, the output of over-voltage circuit can be selectively coupled to the supply rail.
    Type: Application
    Filed: February 16, 2011
    Publication date: August 16, 2012
    Inventors: Nickole Gagne, Kenneth P. Snowdon
  • Publication number: 20120198183
    Abstract: An apparatus comprises a connector configured to receive an electrical contact of an accessory device that is electrically coupled to a resistor of the accessory device, a current source configured to apply a specified current to the resistor to generate a resulting voltage, a comparator configured to receive and compare the resulting voltage to a reference voltage, and a controller configured to store an outcome of the comparison as a bit in a register, to adjust the applied current using the outcome of the comparison, and to determine a resistance value for the resistor using the bit stored in the register.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 2, 2012
    Inventors: Randall Wetzel, Kenneth P. Snowdon, Kenneth O'Brien
  • Publication number: 20120161860
    Abstract: A circuit for selectively providing a signal from a source to a sink is provided. The circuit includes a field effect transistor having a conducting state and a non-conducting state, the field effect transistor having a gate, a source, and a drain. The circuit also includes a first comparator configured to provide a first output based on a difference between a source voltage at the source of the field effect transistor and a first reference voltage. Finally, the circuit includes a switching amplifier configured to apply a first gate voltage to the gate of the field effect transistor as a function of the first output of the first comparator.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Inventor: Kenneth P. Snowdon
  • Publication number: 20120119796
    Abstract: A system comprises a pass switch circuit and a first pass switch activation circuit. The pass switch circuit includes an impedance circuit and a pass transistor having a first source/drain connection, a second source/drain connection, and a gate input. The pass switch circuit passes an electronic signal from the first source/drain connection to the second source/drain connection in response to activation of the gate input. An impedance transfer function of the pass switch circuit is determined at least in part by an impedance of the impedance circuit and the impedance is sized to minimize attenuation of the electronic signal due to the impedance transfer function of the pass switch circuit. The first pass switch activation circuit provides a first activation signal to the gate input in response to an enable signal.
    Type: Application
    Filed: November 12, 2010
    Publication date: May 17, 2012
    Inventor: Kenneth P. Snowdon
  • Publication number: 20110291482
    Abstract: This document discusses, among other things, an electronic circuit and method for defaulting to a valid battery supply to power an electronic device. In an example, an electronic circuit can be configured to receive information about the battery supply (e.g., an internal battery), such as the battery supply voltage (VBAT), and to determine if the battery supply is valid or invalid using the received information (e.g., comparing the VBAT to a threshold). If VBAT is valid, the electronic device can default to receiving power from the battery supply. If VBAT is invalid, the electronic device can receive power from another power supply, such as an external supply.
    Type: Application
    Filed: May 24, 2011
    Publication date: December 1, 2011
    Inventors: James A. Siulinski, Kenneth P. Snowdon
  • Publication number: 20110254618
    Abstract: This document discusses, among other things, an apparatus and method for providing temperature information. In an example, an integrated circuit apparatus can include a first resistor configured to be coupled to a first terminal of a temperature-sensitive resistance, a second resistor configured to be coupled to a second terminal of the temperature-sensitive resistance, and a temperature information circuit configured to receive a first voltage from the first terminal of the temperature-sensitive resistance and a second voltage from the second terminal of the temperature-sensitive resistance. The temperature information circuit can provide the temperature information using the first and second voltages.
    Type: Application
    Filed: January 26, 2011
    Publication date: October 20, 2011
    Inventors: Kenneth P. Snowdon, Roy Yarbrough
  • Publication number: 20110140713
    Abstract: Fuse driver circuits, fuse driver testing circuitry, and methods for testing the fuse driver circuits using the testing circuitry are described. In some embodiments, the fuse driver circuit can be made using a fuse, a NMOS transistor, and a PMOS transistor. The drain of the NMOS transistor can be connected to the negative end of the fuse. The source of the NMOS transistor can be connected to ground. The drain of the PMOS transistor can be connected to a positive end of the fuse. The NMOS and PMOS transistors provide enhanced robustness to the fuse driver circuit in both undervoltage and overvoltage conditions. Other embodiments are also described.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 16, 2011
    Inventors: Kenneth P. Snowdon, James Hall, William Robert Newberry, Roy Yarborough
  • Patent number: 7719324
    Abstract: A low voltage differential signal (LVDS) transmitter with output power control. Internal sensing circuitry monitors output current flow through the termination impedance. When a proper termination impedance is not connected to the output, the resulting improper output current flow (e.g., zero output current when no termination impedance is connected) is detected by the sensing circuitry, which causes the supply current to the output driver circuitry to be reduced. Additionally, further in response to such detection of improper output current flow, the sensing circuitry can cause the output voltage to be limited, e.g., clamped, at a predetermined maximum magnitude.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: May 18, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Ivan Duzevik
  • Patent number: 7542533
    Abstract: Embodiments of the invention include an apparatus and method for continuously calibrating the frequency of a clock and data recovery (CDR) circuit. The apparatus includes a delay arrangement that generates a gating signal, and a gated voltage-controlled oscillator that is enabled by the gating signal. The gated voltage-controlled oscillator generates a recovered clock signal that is based on the data signal input to the CDR circuit. The apparatus also includes a frequency control loop that continuously calibrates the gated voltage-controlled oscillator in such a way that the frequency of the clock signal generated by the gated voltage-controlled oscillator continues to be one half of the period of the data bits in the input data signal and the clock signal remains synchronized to the center of the data state transitions of the input data signal. Alternatively, a secondary frequency control loop adjusts the amount of delay in the frequency control loop.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: June 2, 2009
    Assignee: Agere Systems Inc.
    Inventors: Hrvoje Jasa, Gary D. Polhemus, Kenneth P. Snowdon