Patents by Inventor Kenneth S. Stevens
Kenneth S. Stevens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10310994Abstract: A sequential asynchronous system and a method for operating the same. The method includes operating a first asynchronous finite state machine at a first clock rate and operating a second asynchronous finite state machine at a second clock rate. The method also includes generating, with fork logic, a fork request based on a first state of the first asynchronous finite state machine and receiving, with join logic, the fork request from the fork logic. The method further includes receiving, with the join logic, a communication request from the second asynchronous finite state machine based on a second state of the second asynchronous finite state machine and initiating, with the join logic, a state transition of the second asynchronous finite state machine. The method also includes providing, with the join logic, a join acknowledgement to the fork logic upon completion of the state transition.Type: GrantFiled: February 28, 2017Date of Patent: June 4, 2019Assignee: UNIVERSITY OF UTAH RESEARCH FOUNDATIONInventors: Kenneth S. Stevens, Dipanjan Bhadra
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Patent number: 10084434Abstract: Technology is described for a relative timed clock gated cell. In one example, the relative timed clock gated cell includes a trigger latch and a data clock latch. The trigger latch includes a clock input coupled to a trigger line for transmitting a trigger signal. The trigger latch is configured to generate a data clock signal on an output. The trigger signal is based on a clock signal. The data clock latch includes a clock input coupled to the output of the trigger latch that latches a data input of the data clock latch based on the data clock signal. Various other computing circuitries and methods are also disclosed.Type: GrantFiled: December 9, 2016Date of Patent: September 25, 2018Assignee: UNIVERSITY OF UTAH FOUNDATIONInventors: Kenneth S. Stevens, William Lee
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Publication number: 20180246819Abstract: A sequential asynchronous system and a method for operating the same. The method includes operating a first asynchronous finite state machine at a first clock rate and operating a second asynchronous finite state machine at a second clock rate. The method also includes generating, with fork logic, a fork request based on a first state of the first asynchronous finite state machine and receiving, with join logic, the fork request from the fork logic. The method further includes receiving, with the join logic, a communication request from the second asynchronous finite state machine based on a second state of the second asynchronous finite state machine and initiating, with the join logic, a state transition of the second asynchronous finite state machine. The method also includes providing, with the join logic, a join acknowledgement to the fork logic upon completion of the state transition.Type: ApplicationFiled: February 28, 2017Publication date: August 30, 2018Inventors: Kenneth S. Stevens, Dipanjan Bhadra
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Patent number: 9953120Abstract: Technology for relative timing characterization enabling use of clocked electronic design automation (EDA) tool flows is disclosed. In an example, a method can include a EDA tool identifying a relative timing constraint (RTC) of a cell in a circuit model between a point of divergence (pod) event and two point of convergence (poc) events, wherein the two poc events include a first poc event (poc0) and a second poc event (poc1). The EDA tool can generate a maximum target delay for a first poc event path between the pod event and the first poc event. The EDA tool can generate a minimum target delay for a second poc event path between the pod event and the second poc event. The EDA tool can then optimize the circuit model using the maximum target delay and the minimum target delay.Type: GrantFiled: July 18, 2013Date of Patent: April 24, 2018Assignee: University of Utah Research FoundationInventor: Kenneth S. Stevens
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Patent number: 9753486Abstract: Technology is described for an asynchronous wrapper circuit for a clock gating cell (CGC). In one example, the asynchronous wrapper cell for CGC includes circuitry configured to (1) sample a data channel via sampling circuitry for a communication start signal to enable the CGC to start a gated clock for a data message on the data channel, and (2) reset an enable of the CGC to an idle mode via idle mode control circuitry after the data message has been clocked via the CGC through function cell circuitry. The idle mode control circuitry generates an output for the sampling circuitry from the function cell. Various other computing circuitries are also disclosed.Type: GrantFiled: June 15, 2015Date of Patent: September 5, 2017Assignee: UNIVERSITY OF UTAH RESEARCH FOUNDATIONInventors: Kenneth S. Stevens, Dipanjan Bhadra
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Publication number: 20170244392Abstract: Technology is described for a relative timed clock gated cell. In one example, the relative timed clock gated cell includes a trigger latch and a data clock latch. The trigger latch includes a clock input coupled to a trigger line for transmitting a trigger signal. The trigger latch is configured to generate a data clock signal on an output. The trigger signal is based on a clock signal. The data clock latch includes a clock input coupled to the output of the trigger latch that latches a data input of the data clock latch based on the data clock signal. Various other computing circuitries and methods are also disclosed.Type: ApplicationFiled: December 9, 2016Publication date: August 24, 2017Inventors: Kenneth S. Stevens, William Lee
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Patent number: 9548736Abstract: Technology is described for a relative timed clock gated cell. In one example, the relative timed clock gated cell includes a trigger latch and a data clock latch. The trigger latch includes a clock input coupled to a trigger line for transmitting a trigger signal. The trigger latch is configured to generate a data clock signal on an output. The trigger signal is based on a clock signal. The data clock latch includes a clock input coupled to the output of the trigger latch that latches a data input of the data clock latch based on the data clock signal. Various other computing circuitries and methods are also disclosed.Type: GrantFiled: June 15, 2015Date of Patent: January 17, 2017Assignee: The University of Utah Research FoundationInventors: Kenneth S. Stevens, William Lee
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Publication number: 20160365857Abstract: Technology is described for a relative timed clock gated cell. In one example, the relative timed clock gated cell includes a trigger latch and a data clock latch. The trigger latch includes a clock input coupled to a trigger line for transmitting a trigger signal. The trigger latch is configured to generate a data clock signal on an output. The trigger signal is based on a clock signal. The data clock latch includes a clock input coupled to the output of the trigger latch that latches a data input of the data clock latch based on the data clock signal. Various other computing circuitries and methods are also disclosed.Type: ApplicationFiled: June 15, 2015Publication date: December 15, 2016Inventors: Kenneth S. Stevens, William Lee
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Publication number: 20160363955Abstract: Technology is described for an asynchronous wrapper circuit for a clock gating cell (CGC). In one example, the asynchronous wrapper cell for CGC includes circuitry configured to (1) sample a data channel via sampling circuitry for a communication start signal to enable the CGC to start a gated clock for a data message on the data channel, and (2) reset an enable of the CGC to an idle mode via idle mode control circuitry after the data message has been clocked via the CGC through function cell circuitry. The idle mode control circuitry generates an output for the sampling circuitry from the function cell. Various other computing circuitries are also disclosed.Type: ApplicationFiled: June 15, 2015Publication date: December 15, 2016Inventors: Kenneth S. Stevens, Dipanjan Bhadra
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Publication number: 20150026653Abstract: Technology for relative timing characterization enabling use of clocked electronic design automation (EDA) tool flows is disclosed. In an example, a method can include a EDA tool identifying a relative timing constraint (RTC) of a cell in a circuit model between a point of divergence (pod) event and two point of convergence (poc) events, wherein the two poc events include a first poc event (poc0) and a second poc event (poc1). The EDA tool can generate a maximum target delay for a first poc event path between the pod event and the first poc event. The EDA tool can generate a minimum target delay for a second poc event path between the pod event and the second poc event. The EDA tool can then optimize the circuit model using the maximum target delay and the minimum target delay.Type: ApplicationFiled: July 18, 2013Publication date: January 22, 2015Inventor: KENNETH S. STEVENS
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Publication number: 20140165022Abstract: Technology for generating a relative timing architecture using a relative timed module is disclosed. In an example, an electronic design automation (EDA) tool enabled for clocked tool flows can include computer circuitry configured to: Generate a hardware description language (HDL) integrated circuit (IC) architecture using the relative timed module; map a relative timing constraint on to a relative timed instance of the relative timed module; and generate a timing target for each relative timing constraint.Type: ApplicationFiled: July 18, 2013Publication date: June 12, 2014Inventor: KENNETH S. STEVENS
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Publication number: 20130097567Abstract: The timing cycles in a circuit design are identified and cut such that timing constraint paths in the circuit design are preserved. Timing cycles in the circuit design may be identified by traversing an adjacency list data structure, in which elements of the circuit design are represented as vertices interconnected by edges. Timing constraint paths may be distinguished from false timing paths using timing analysis, such as a greatest common path heuristic. Timing constraint paths may be marked as “constrained” to prevent these paths from being cut. With the cycles and timing constraint paths identified, cuts may be selected that cut the identified timing cycles while preserving the timing constraint paths. The cycle cuts allow the circuit design to be correctly processed within a conventional CAD tool design flow.Type: ApplicationFiled: December 5, 2012Publication date: April 18, 2013Inventors: Kenneth S. Stevens, Vikas Vij
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Patent number: 8365116Abstract: The timing cycles in a circuit design are identified and cut such that timing constraint paths in the circuit design are preserved. Timing cycles in the circuit design may be identified by traversing an adjacency list data structure, in which elements of the circuit design are represented as vertices interconnected by edges. Timing constraint paths may be distinguished from false timing paths using timing analysis, such as a greatest common path heuristic. Timing constraint paths may be marked as “constrained” to prevent these paths from being cut. With the cycles and timing constraint paths identified, cuts may be selected that cut the identified timing cycles while preserving the timing constraint paths. The cycle cuts allow the circuit design to be correctly processed within a conventional CAD tool design flow.Type: GrantFiled: December 6, 2010Date of Patent: January 29, 2013Assignee: University of Utah Research FoundationInventors: Kenneth S. Stevens, Vikas Vij
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Patent number: 8321825Abstract: A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, multiple trace status tables are received, each containing a trace error identified by a formal verification engine that was utilized to perform a RT verification on an integrated circuit design. An error causing signal is then recognized for each of the trace errors. For each of error causing signals, two associating signals are identified, and the two associating signals are then utilized to locate a common point of convergence (POC). The POC is further utilized to locate a common point of divergence (POD), and an RT constraint can be generated based on the identified POC and POD. All the generated RT constraints are applied to constrain the integrated circuit design such that the integrated circuit design is able to pass RT verifications in the future without any timing violations.Type: GrantFiled: May 22, 2012Date of Patent: November 27, 2012Assignee: University of UtahInventors: Kenneth S. Stevens, Yang Xu
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Publication number: 20120254815Abstract: A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, multiple trace status tables are received, each containing a trace error identified by a formal verification engine that was utilized to perform a RT verification on an integrated circuit design. An error causing signal is then recognized for each of the trace errors. For each of error causing signals, two associating signals are identified, and the two associating signals are then utilized to locate a common point of convergence (POC). The POC is further utilized to locate a common point of divergence (POD), and an RT constraint can be generated based on the identified POC and POD. All the generated RT constraints are applied to constrain the integrated circuit design such that the integrated circuit design is able to pass RT verifications in the future without any timing violations.Type: ApplicationFiled: May 22, 2012Publication date: October 4, 2012Inventors: Kenneth S. Stevens, Yang Xu
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Patent number: 8239796Abstract: A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, multiple trace status tables are received, and each of the trace status tables contains a trace error identified by a formal verification engine that was utilized to perform a relative timing (RT) verification on an integrated circuit design. An error causing signal is then recognized for each of the trace errors. For each of error causing signals, two associating signals are identified, and the two associating signals are then utilized to locate a common point of convergence (POC). The POC is further utilized to locate a common point of divergence (POD), and an RT constraint can be generated based on the identified POC and POD. All the generated RT constraints are applied to constrain the integrated circuit design such that the integrated circuit design is able to pass RT verifications in the future without any timing violations.Type: GrantFiled: March 2, 2010Date of Patent: August 7, 2012Assignee: University of UtahInventors: Kenneth S. Stevens, Yang Xu
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Publication number: 20120144359Abstract: The timing cycles in a circuit design are identified and cut such that timing constraint paths in the circuit design are preserved. Timing cycles in the circuit design may be identified by traversing an adjacency list data structure, in which elements of the circuit design are represented as vertices interconnected by edges. Timing constraint paths may be distinguished from false timing paths using timing analysis, such as a greatest common path heuristic. Timing constraint paths may be marked as “constrained” to prevent these paths from being cut. With the cycles and timing constraint paths identified, cuts may be selected that cut the identified timing cycles while preserving the timing constraint paths. The cycle cuts allow the circuit design to be correctly processed within a conventional CAD tool design flow.Type: ApplicationFiled: December 6, 2010Publication date: June 7, 2012Inventors: Kenneth S. Stevens, Vikas Vij
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Patent number: 8065647Abstract: A method of designing an asynchronous integrated circuit is provided. A global clock network of a synchronous circuit is replaced with a plurality of handshaking circuits. Data validity is encoded into a communication path between a first pipeline stage and a second pipeline stage of the synchronous circuit. A control logic for the first pipeline stage is implemented using a template that contains characterization information for timing to generate an asynchronous circuit design.Type: GrantFiled: October 17, 2008Date of Patent: November 22, 2011Assignee: The University of Utah Research FoundationInventor: Kenneth S. Stevens
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Publication number: 20110161902Abstract: A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, mulitple trace status tables are received, and each of the trace status tables contains a trace error identified by a formal verification engine that was utilized to perform a relative timing (RT) verification on an integrated circuit design. An error causing signal is then recognized for each of the trace errors. For each of error causing signals, two associating signals are identified, and the two associating signals are then utilized to locate a common point of convergence (POC). The POC is further utilized to locate a common point of divergence (POD), and an RT constraint can be generated based on the identified POC and POD. All the generated RT constraints are applied to constrain the integrated circuit design such that the integrated circuit design is able to pass RT verifications in the future without any timing violations.Type: ApplicationFiled: March 2, 2010Publication date: June 30, 2011Inventors: Kenneth S. Stevens, Yang Yu
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Publication number: 20090106719Abstract: A method of designing an asynchronous integrated circuit is provided. A global clock network of a synchronous circuit is replaced with a plurality of handshaking circuits. Data validity is encoded into a communication path between a first pipeline stage and a second pipeline stage of the synchronous circuit. A control logic for the first pipeline stage is implemented using a template that contains characterization information for timing to generate an asynchronous circuit design.Type: ApplicationFiled: October 17, 2008Publication date: April 23, 2009Inventor: Kenneth S. Stevens