Patents by Inventor Kenneth T. Chin
Kenneth T. Chin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11360782Abstract: An apparatus includes a subsystem, a first processor, a memory, a circuit and a second processor. The first processor is to execute bootstrap instructions, and the memory is to store second instructions. The circuit is to hold the first processor in reset in response to the apparatus being powered on; and the second processor is to, while the first processor is held in reset, execute the second instructions to initialize the subsystem.Type: GrantFiled: January 31, 2020Date of Patent: June 14, 2022Assignee: Hewlett Packard Enterprise Development LPInventors: Naysen Robertson, Kenneth T. Chin, Theodore F. Emerson
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Patent number: 11138140Abstract: An apparatus includes a plurality of subsystems, including a first subsystem and a second subsystem. The apparatus includes a master processor to, in response to a power on of the apparatus, execute first instructions to configure the first subsystem and provide second instructions. The apparatus further includes a slave processor to, prior to the boot of the apparatus, receive the second instructions from the master processor and execute the second instructions to configure the second subsystem.Type: GrantFiled: January 31, 2020Date of Patent: October 5, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Naysen Robertson, Kenneth T. Chin, Theodore F. Emerson
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Publication number: 20210240485Abstract: An apparatus includes a subsystem, a first processor, a memory, a circuit and a second processor. The first processor is to execute bootstrap instructions, and the memory is to store second instructions. The circuit is to hold the first processor in reset in response to the apparatus being powered on; and the second processor is to, while the first processor is held in reset, execute the second instructions to initialize the subsystem.Type: ApplicationFiled: January 31, 2020Publication date: August 5, 2021Inventors: Naysen Robertson, Kenneth T. Chin, Theodore F. Emerson
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Publication number: 20210240646Abstract: An apparatus includes a plurality of subsystems, including a first subsystem and a second subsystem. The apparatus includes a master processor to, in response to a power on of the apparatus, execute first instructions to configure the first subsystem and provide second instructions. The apparatus further includes a slave processor to, prior to the boot of the apparatus, receive the second instructions from the master processor and execute the second instructions to configure the second subsystem.Type: ApplicationFiled: January 31, 2020Publication date: August 5, 2021Inventors: Naysen Robertson, Kenneth T. Chin, Theodore F. Emerson
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Patent number: 10404244Abstract: An example device in accordance with an aspect of the present disclosure includes a first stage and an accumulator. The first stage is based on digital logic and integer arithmetic to scale a reference clock by a configurable ratio of integers according to a line drawing technique to obtain an output clock. The accumulator is to store an accumulated error of a variable used in the line drawing technique.Type: GrantFiled: March 31, 2017Date of Patent: September 3, 2019Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Christopher Wesneski, Theodore F. Emerson, Kenneth T. Chin
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Patent number: 10372400Abstract: An apparatus includes a plurality of compute nodes and a baseboard management controller that is shared by the plurality of compute nodes to manage video for the compute nodes. The baseboard management controller includes video controllers that are associated with the plurality of compute nodes and at least one resource that is shared by the video controllers.Type: GrantFiled: May 21, 2015Date of Patent: August 6, 2019Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Theodore F. Emerson, David F. Heinrich, Kenneth T. Chin
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Publication number: 20180287621Abstract: An example device in accordance with an aspect of the present disclosure includes a first stage and an accumulator. The first stage is based on digital logic and integer arithmetic to scale a reference clock by a configurable ratio of integers according to a line drawing technique to obtain an output clock. The accumulator is to store an accumulated error of a variable used in the line drawing technique.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Christopher Wesneski, Theodore F. Emerson, Kenneth T. Chin
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Publication number: 20180074777Abstract: An apparatus includes a plurality of compute nodes and a baseboard management controller that is shared by the plurality of compute nodes to manage video for the compute nodes. The baseboard management controller includes video controllers that are associated with the plurality of compute nodes and at least one resource that is shared by the video controllers.Type: ApplicationFiled: May 21, 2015Publication date: March 15, 2018Inventors: Theodore F. Emerson, David F. Heinrich, Kenneth T. Chin
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Patent number: 8174977Abstract: A network node within a network includes a first receive buffer, first buffer management, a second receive buffer and second buffer management. The first buffer management performs link level credit based flow control for network packets that the first buffer management places in the first receive buffer. The second buffer management performs end-to-end credit based flow control for network packets that the second buffer management receives from the first receive buffer and processes before placing data in the second receive buffer.Type: GrantFiled: July 6, 2007Date of Patent: May 8, 2012Assignee: Hewlett-Packard Development Company, L.P.Inventors: Paul V. Brownell, David L. Matthews, James Xuan Dinh, Hubert E. Brinkmann, Dwight D. Riley, Hahn Vo Norden, Kenneth T. Chin
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Patent number: 7876759Abstract: A system is provided comprising a fabric coupling together a plurality of computing devices, wherein the fabric transfers a stream of packets between the computing devices. Each computing device comprises a Quality of Service (“QOS”) filter that monitors incoming packets to filter out packets of a maintenance type and permit transfer of packets of a transaction type.Type: GrantFiled: July 11, 2007Date of Patent: January 25, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Hahn Vo Norden, Hubert E. Brinkmann, Paul V. Brownell, Kenneth T. Chin, James Dinh, David L. Matthews, Dwight D. Riley
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Publication number: 20090016348Abstract: A system is provided comprising a fabric coupling together a plurality of computing devices, wherein the fabric transfers a stream of packets between the computing devices. Each computing device comprises a Quality of Service (“QOS”) filter that monitors incoming packets to filter out packets of a maintenance type and permit transfer of packets of a transaction type.Type: ApplicationFiled: July 11, 2007Publication date: January 15, 2009Inventors: Hahn Vo Norden, Hubert E. Brinkmann, Paul V. Brownell, Kenneth T. Chin, James Dinh, David L. Matthews, Dwight D. Riley
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Publication number: 20090010159Abstract: A network node within a network includes a first receive buffer, first buffer management, a second receive buffer and second buffer management. The first buffer management performs link level credit based flow control for network packets that the first buffer management places in the first receive buffer. The second buffer management performs end-to-end credit based flow control for network packets that the second buffer management receives from the first receive buffer and processes before placing data in the second receive buffer.Type: ApplicationFiled: July 6, 2007Publication date: January 8, 2009Inventors: Paul V. Brownell, David L. Matthews, James Xuan Dinh, Hubert E. Brinkmann, Dwight D. Riley, Hahn Vo Norden, Kenneth T. Chin
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Patent number: 6961800Abstract: Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.Type: GrantFiled: September 28, 2001Date of Patent: November 1, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Robert A. Lester, Kenneth T. Chin, Jim Blocker, John E. Larson, Phillip M. Jones, Paul B. Rawlins
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Patent number: 6829665Abstract: A technique for optimizing cycle time in maintaining cache coherency. Specifically, a method and apparatus are provided to optimize the processing of requests in a multi-processor-bus system which implements a snoop-based coherency scheme. The acts of snooping a bus for a first address and searching a posting queue for the next address to be snooped are performed simultaneously to minimize the request cycle time.Type: GrantFiled: September 28, 2001Date of Patent: December 7, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Phillip M. Jones, Paul B. Rawlins, Kenneth T. Chin
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Publication number: 20030065844Abstract: Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventors: Robert A. Lester, Kenneth T. Chin, Jim Blocker, John E. Larson, Phillip M. Jones, Paul B. Rawlins
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Publication number: 20030065860Abstract: An internal bus structure for a multi-processor-bus system. More specifically, an internal bus protocol/structure is described. The internal bus structure includes unidirectional, point-to-point connections between control modules. The individual buses carry unique transactions corresponding to a request. Each transaction includes an identification tag. The present protocol provides for efficient communication between processors, peripheral devices, memory and coherency modules. The present protocol and design scheme is generic in that the techniques are scalable and re-usable.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventors: Robert A. Lester, Kenneth T. Chin, Jim Blocker, John E. Larson, Phillip M. Jones, Paul B. Rawlins
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Publication number: 20030065843Abstract: A technique for optimizing cycle time in maintaining cache coherency. Specifically, a method and apparatus are provided to optimize the processing of requests in a multi-processor-bus system which implements a snoop-based coherency scheme. The acts of snooping a bus for a first address and searching a posting queue for the next address to be snooped are performed simultaneously to minimize the request cycle time.Type: ApplicationFiled: September 28, 2001Publication date: April 3, 2003Inventors: Phillip M. Jones, Paul B. Rawlins, Kenneth T. Chin
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Patent number: 6505260Abstract: A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests.Type: GrantFiled: February 15, 2001Date of Patent: January 7, 2003Assignee: Compaq Information Technologies Group, L.P.Inventors: Kenneth T. Chin, C. Kevin Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo, Jeffrey C. Stevens
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Patent number: 6356972Abstract: A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues.Type: GrantFiled: January 19, 2001Date of Patent: March 12, 2002Assignee: Compaq Information Technologies Group, LPInventors: Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo
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Patent number: 6286083Abstract: A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests.Type: GrantFiled: July 8, 1998Date of Patent: September 4, 2001Assignee: Compaq Computer CorporationInventors: Kenneth T. Chin, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo, Jeffrey C. Stevens, Michael J. Collins, C. Kevin Coffee