Patents by Inventor Kensuke Ishikawa

Kensuke Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7018919
    Abstract: In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: March 28, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Kensuke Ishikawa, Tatsuyuki Saito, Masanori Miyauchi, Toshio Saito, Hiroshi Ashihara
  • Publication number: 20060006543
    Abstract: A reliable semiconductor device having a multilayer wiring structure formed of copper as a main component material, which constrains occurrence of voids caused by stress migration. In the multilayer wiring structure, a first insulation layer having a high barrier property and a compression stress, and making contact with the upper surface of a first wiring made of copper as a main component material, a second insulation film having a tensile stress, and a third insulation film having a dielectric constant which is lower than those of the first and second insulation film, are laminated one upon another in the mentioned order as viewed the bottom thereof, and a via hole is formed piercing thorough the first insulation film, the second insulation film and the third insulation film, making contact with the first wiring.
    Type: Application
    Filed: June 17, 2005
    Publication date: January 12, 2006
    Applicant: Hitachi, Ltd.
    Inventors: Hiromi Shimazu, Tomio Iwasaki, Hiroyuki Ohta, Kensuke Ishikawa, Osamu Inoue, Takayuki Oshima
  • Patent number: 6838772
    Abstract: A semiconductor device has a first insulating film deposited over a semiconductor substrate, an interconnect opening portion formed in the first insulating film, an interconnect disposed in the interconnect opening portion, and a second insulating film formed over the first insulating film and the interconnect. The interconnect has a first conductor film, a second conductor film formed via the first conductor film and comprised of one of titanium silicon nitride, tantalum silicon nitride, tantalum nitride and titanium nitride, a third conductor film formed via the first and second conductor films and comprised of a material having good adhesion with copper; and a fourth conductor film formed via the first, second and third conductor conductor film having a copper as a main component. Thus, it is possible to improve adhesion between a conductor film composed mainly of copper and another conductor film having a copper-diffusion barrier function in the interconnect.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: January 4, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Toshio Saitoh, Kensuke Ishikawa, Hiroshi Ashihara, Tatsuyuki Saito
  • Publication number: 20040227242
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: March 24, 2004
    Publication date: November 18, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Publication number: 20030214043
    Abstract: Provided is a semiconductor device comprising a first insulating film deposited over a semiconductor substrate, an interconnect opening portion formed in the first insulating film, an interconnect disposed in the interconnect opening portion, and a second insulating film formed over the first insulating film and the interconnect, said interconnect having a first conductor film, a second conductor film formed via the first conductor film by chemical vapor deposition or ALS and comprised of any one of titanium silicon nitride, tantalum silicon nitride, tantalum nitride and titanium nitride, a third conductor film formed via the first and second conductor films and comprised of a material having good adhesion with copper; and a fourth conductor film formed via the first, second and third conductor films and having copper as a main component.
    Type: Application
    Filed: May 15, 2003
    Publication date: November 20, 2003
    Inventors: Toshio Saitoh, Kensuke Ishikawa, Hiroshi Ashihara, Tatsuyuki Saito
  • Publication number: 20030102565
    Abstract: In a manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.
    Type: Application
    Filed: December 24, 2002
    Publication date: June 5, 2003
    Inventors: Kensuke Ishikawa, Tatsuyuki Saito, Masanori Miyauchi, Toshio Saito, Hiroshi Ashihara
  • Publication number: 20030067079
    Abstract: Provided are a manufacturing method of a semiconductor integrated circuit device, which comprises forming an interconnect trench and a contact hole in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, forming a barrier film inside of the trench and hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, forming a copper film over the barrier film, and forming the second-level interconnect and a connector portion (plug) by polishing by CMP; and the semiconductor integrated circuit device manufactured by this method.
    Type: Application
    Filed: October 4, 2002
    Publication date: April 10, 2003
    Inventors: Kensuke Ishikawa, Tatsuyuki Saito, Masanori Miyauchi, Toshio Saito, Hiroshi Ashihara