Patents by Inventor Kent Kuohua Chang

Kent Kuohua Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6812099
    Abstract: A method for fabricating a non-volatile memory having a P-type floating gate is described. A tunneling layer is formed on a substrate and then a first patterned polysilicon layer is formed on the tunneling layer. A buried drain is formed in the substrate beside the first polysilicon layer and then an insulating structure is formed on the tunneling layer on the buried drain. Thereafter, a second polysilicon layer is formed on the first polysilicon layer to constitute a floating gate together with the first polysilicon layer. A P-type ion is implanted into the second polysilicon layer and then a dielectric layer and a control gate are sequentially formed on the floating gate. A thermal process is then performed to make the P-type, ion in the second polysilicon layer diffuse into the first polysilicon layer.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: November 2, 2004
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Hung-Sui Lin, Nian-Kai Zous, Tao-Cheng Lu, Kent Kuohua Chang
  • Patent number: 6797567
    Abstract: A fabrication method for a read only memory device with a high dielectric constant tunneling dielectric layer, wherein this method provides forming a tunneling dielectric layer on a substrate, wherein the tunneling dielectric layer is formed with HfSiON or HfOxNy. An electron trapping layer and a top oxide layer are sequentially formed over the tunneling dielectric layer. Thereafter, the oxide layer, the electron trapping layer and the tunneling dielectric layer are patterned to form a plurality of stacked structures, followed by forming doped regions in the substrate between the stacked structures. Buried drain oxide layers are further formed over the surface of the doped regions, followed by forming a patterned conductive layer as the word line for the read only memory device.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: September 28, 2004
    Assignee: Macronix International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Patent number: 6777285
    Abstract: A memory device and a method for fabricating the same are described. The memory device includes a substrate, buried bit lines, word line structures, a dielectric layer, conductive lines in trenches and self-aligned contacts. The buried bit lines are located in the substrate, and the word line structures are disposed on the substrate crossing over the buried bit lines. Each word line structure consists of a word line, a gate oxide layer, a capping layer and a spacer. Each conductive line is disposed in the dielectric layer and over a buried bit line, and crosses over the capping layers. The dielectric layer is disposed between the word line structures and between the conductive lines. Each self-aligned contact is disposed under a conductive line and between two adjacent word lines to electrically connect the conductive line and the corresponding buried bit line.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: August 17, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Weng-Hsing Huang, Kent Kuohua Chang
  • Patent number: 6777742
    Abstract: A radiation resistant hexagonal gate flash memory cell. The flash memory cell includes a substrate, a source region, a drain region and a gate structure. A channel region is also formed in the substrate between the source region and the drain region. The gate structure is located above the substrate between the source region and the drain region. The gate structure further includes an oxide-nitride-oxide composite layer over the substrate. In a direction perpendicular to the channel, width of the gate structure increases gradually from the source region towards a pre-determined location and decreases towards the drain region thereafter. When the flash memory cell is subjected to radiation illumination, electron-hole pairs thus generated will be injected into the substrate without passing into the nitride layer.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: August 17, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Fuh-cheng Jong, Kent Kuohua Chang
  • Patent number: 6773933
    Abstract: A method of boosting wafer-cleaning efficiency and increasing process yield. Different types of process particles are deposited on a test wafer. The test wafer is cleaned in a cleaning operation. The test wafer is scanned to determine the types of process particles that are completely removed and the types of process particles that remain over the test wafer. The results of wafer scanning are used to provide an assessment of the efficiency of the cleaning operation. Operation parameters of the cleaning operation are adjusted to maximize the wafer-cleaning efficiency.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: August 10, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Szu-Tsun Ma, Kent Kuohua Chang
  • Publication number: 20040152305
    Abstract: A method of preventing the corrosion of tungsten plug within a substrate in the process of manufacturing a semiconductor device. The tungsten plug within the substrate is coupled to a conductive line on the substrate. The process includes treating the substrate with a charge neutralizer so that charges accumulated on the surface of the conductive line during etching is removed and conducting a wet-cleaning operation thereafter.
    Type: Application
    Filed: January 30, 2003
    Publication date: August 5, 2004
    Inventors: CHUNG-LUNG YIU, SZU-TSUN MA, KENT KUOHUA CHANG
  • Publication number: 20040137683
    Abstract: A method of fabricating a multi-bit flash memory, having a control gate, a floating gate, a source region, a drain region and a channel region. An isolation region is formed in the floating gate to partition the floating gate into a plurality of conductive blocks. The conductive blocks are arranged in an array with rows extending from the source region to the drain region. Each row of the array has two conductive blocks. Before any data is written to the flash memory, the channel regions under the conductive blocks of the same row have the same threshold voltage, while the channel regions under the conductive blocks of different rows have different threshold voltage.
    Type: Application
    Filed: January 20, 2004
    Publication date: July 15, 2004
    Inventor: Kent Kuohua Chang
  • Patent number: 6762467
    Abstract: A nonvolatile memory cell for prevention from second bit effect comprises a pair of source/drain regions arranged with a channel therebetween, a programmable layer above the channel, and a gate conductor above the programmable layer. The memory cell is characterized in that the programmable layer has a maximum width substantially larger than the boundary widths between the programmable layer and the source/drain regions. The programmable layer comprises a trapping dielectric layer inserted between two insulator layers, and the trapping dielectric preferably comprises a nitride or an oxide having buried polysilicon islands.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: July 13, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Fuh-Cheng Jong, Kent Kuohua Chang
  • Publication number: 20040126962
    Abstract: A method of fabricating a shallow trench isolation. A wafer on which a mask layer is formed is provided. A blank wafer is provided and disposed in an etching machine to perform an etching process. Whether the blank wafer contains a defect is inspected. If the number of defects occurring on the blank wafer is within an acceptable quantity, the wafer is disposed in the etching machine for performing an etching process and defining a trench. The trench is then filled with an insulation layer. The mask layer is removed to form a shallow trench isolation.
    Type: Application
    Filed: May 8, 2003
    Publication date: July 1, 2004
    Inventors: Szu-Tsun Ma, Kent Kuohua Chang
  • Publication number: 20040121592
    Abstract: A method for fabricating a metal silicide layer includes forming a dielectric layer on a substrate, followed by forming a polysilicon material conductive layer on the dielectric layer. An adhesion layer is then formed on the conductive layer, wherein the adhesion layer is a nitrogen rich layer or a nitrogen ion implanted layer. A metal silicide layer is then formed on the adhesion layer. The adhesion between the metal silicide layer and the conductive layer is more desirable due the adhesion layer.
    Type: Application
    Filed: December 24, 2002
    Publication date: June 24, 2004
    Inventor: KENT KUOHUA CHANG
  • Publication number: 20040121544
    Abstract: A fabrication method for a read only memory device with a high dielectric constant tunneling dielectric layer, wherein this method provides forming a tunneling dielectric layer on a substrate, wherein the tunneling dielectric layer is formed with HfSiON or HfOxNy. An electron trapping layer and a top oxide layer are sequentially formed over the tunneling dielectric layer. Thereafter, the oxide layer, the electron trapping layer and the tunneling dielectric layer are patterned to form a plurality of stacked structures, followed by forming doped regions in the substrate between the stacked structures. Buried drain oxide layers are further formed over the surface of the doped regions, followed by forming a patterned conductive layer as the word line for the read only memory device.
    Type: Application
    Filed: December 24, 2002
    Publication date: June 24, 2004
    Inventor: Kent Kuohua Chang
  • Publication number: 20040121542
    Abstract: A silicon nitride read only memory, having a control gate formed on a substrate, a source region and a drain region formed in the substrate at two sides of the control gate, a charge capture layer between the control gate and the substrate, a stacked dielectric layer between the control gate and the charge capture layer, and a channel in the substrate under the charge capture layer between the source and drain regions. By forming the silicon oxide/silicon nitride/silicon oxide stacked dielectric layer, the reliability of the memory device is enhanced since silicon nitride provides a better effect for isolating the charge capture layer and the control gate.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 24, 2004
    Inventor: Kent Kuohua Chang
  • Publication number: 20040119108
    Abstract: A silicon nitride read-only-memory structure is provided. The silicon nitride read-only-memory includes a control gate over a substrate, a source region and a drain region in the substrate on each side of the control gate, a charge-trapping layer between the control gate and the substrate and a channel layer in the substrate underneath the charge-trapping layer and between the source region and the drain region. The charge-trapping layer further includes an isolation region. The isolation region partitions the charge-trapping layer into a source side charge-trapping block and a drain side charge-trapping block so that a two-bit structure is formed.
    Type: Application
    Filed: December 24, 2002
    Publication date: June 24, 2004
    Inventor: Kent Kuohua Chang
  • Publication number: 20040115888
    Abstract: A manufacturing method for a semiconductor device is provided, wherein a silicon germanium (Si1-xGex; SiGe) layer and a strained silicon layer are sequentially formed on a semiconductor substrate. A gate oxide layer and a gate structure are further formed on the strained silicon layer. The gate structure and the strained silicon layer are heavily doped with n-type dopants to form a compressed gate and source/drain regions, respectively. A cap layer is further formed over the semiconductor substrate, followed by conducting an annealing process. The cap layer is subsequently removed.
    Type: Application
    Filed: September 10, 2003
    Publication date: June 17, 2004
    Inventor: Kent Kuohua Chang
  • Publication number: 20040110344
    Abstract: A memory device and a method for fabricating the same are described. The memory device includes a substrate, buried bit lines, word line structures, a dielectric layer, conductive lines in trenches and self-aligned contacts. The buried bit lines are located in the substrate, and the word line structures are disposed on the substrate crossing over the buried bit lines. Each word line structure consists of a word line, a gate oxide layer, a capping layer and a spacer. Each conductive line is disposed in the dielectric layer and over a buried bit line, and crosses over the capping layers. The dielectric layer is disposed between the word line structures and between the conductive lines. Each self-aligned contact is disposed under a conductive line and between two adjacent word lines to electrically connect the conductive line and the corresponding buried bit line.
    Type: Application
    Filed: July 15, 2003
    Publication date: June 10, 2004
    Inventors: Weng-Hsing Huang, Kent Kuohua Chang
  • Patent number: 6737324
    Abstract: A method for fabricating a raised source/drain of a semiconductor device is described. A gate structure is formed on a substrate, and then a source/drain with a shallow-junction is formed in the substrate beside the gate structure. A spacer is formed on the sidewalls of the gate structure. Thereafter, an elevated layer is formed on the gate structure and the source/drain with a shallow junction, wherein the elevated layer formed on the source/drain serves as an elevated source/drain layer.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: May 18, 2004
    Assignee: Macronix, International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Patent number: 6720613
    Abstract: A method of fabricating a multi-bit flash memory, having a control gate, a floating gate, a source region, a drain region and a channel region. An isolation region is formed in the floating gate to partition the floating gate into a plurality of conductive blocks. The conductive blocks are arranged in an array with rows extending from the source region to the drain region. Each row of the array has two conductive blocks. Before any data is written to the flash memory, the channel regions under the conductive blocks of the same row have the same threshold voltage, while the channel regions under the conductive blocks of different rows have different threshold voltage.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: April 13, 2004
    Assignee: Macronix International Co., Ltd.
    Inventor: Kent Kuohua Chang
  • Patent number: 6713388
    Abstract: A memory device is formed on a silicon substrate. A blocking layer is thereafter formed to cover a stacked gate of the memory device. A gettering layer is formed on the blocking layer followed by planarizing of the gettering layer to a predetermined thickness. A first barrier layer is then formed on the gettering layer. A contact hole is formed to penetrate through the first barrier layer, the gettering layer and the blocking layer down to the surface of the memory device. Following that, a second barrier layer is created to cover the first barrier layer and the contact hole. Finally, portions of the second barrier layer are etched back to make a barrier spacer on the side wall of the contact hole. Therein, the first barrier layer and the barrier spacer prevent mobile atoms from vertically diffusing and laterally diffusing, respectively, into the memory device.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: March 30, 2004
    Assignee: Macronix International Co. Ltd.
    Inventors: Uway Tseng, Ching-Yu Chang, Kent Kuohua Chang
  • Patent number: 6710381
    Abstract: The present invention provides a memory structure, comprising: a substrate; a gate oxide layer disposed on a portion of the substrate; a gate structure disposed on the gate oxide layer; a buried bit line disposed in the substrate along both sides of the gate structures; a raised line disposed on the burled bit line; an isolating spacer disposed on both sidewalls of the gate structure and a word line disposed over the substrate in a direction perpendicular to the buried bit line; and an insulation layer disposed on a top of the raised line to electrically isolate the raised line and the word line.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: March 23, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Weng-Hsing Huang, Kent Kuohua Chang
  • Patent number: 6706612
    Abstract: A method for fabricating a shallow trench isolation structure includes forming a hard mask layer over a substrate. An ion bombardment step is further performed on the surface of the hard mask layer, followed by forming a patterned photoresist layer on the surface of the hard mask layer. Thereafter, the hard mask layer is patterned using the photoresist layer as an etching mask. An etching process is further performed to form a trench in the substrate. The photoresist layer is then removed, followed by filling an insulation layer in the trench. After this, the hard mask is removed to complete the fabrication of a shallow trench isolation region.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: March 16, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Szu-Tsun Ma, Kent Kuohua Chang