Patents by Inventor Kent Kuohua Chang

Kent Kuohua Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020173104
    Abstract: The present invention shows a method of fabricating a MOS transistor on the substrate of a semiconductor wafer and of preventing the gate depletion effects occurring in the MOS transistor. The method involves first forming a silicon oxide layer on the substrate. Then an amorphous silicon layer is formed on the silicon oxide layer followed by forming a silicon germanium (Si1-xGex, x=0.05˜1.0) layer on the amorphous silicon layer. Thereafter, an etching process removes portions of the silicon germanium layer and the amorphous silicon layer so as to form gates of the MOS transistor on the substrate. Finally, a spacer is formed around each gate and a source and a drain of each MOS transistor is formed in the substrate.
    Type: Application
    Filed: May 17, 2001
    Publication date: November 21, 2002
    Inventor: Kent Kuohua Chang
  • Publication number: 20020168875
    Abstract: The present invention fabricates an oxide-nitride-oxide (ONO) layer of an NROM. A first oxide layer is formed on the surface of the substrate of a semiconductor wafer. Then two CVD processes are performed to respectively form a first nitride layer and a second nitride layer on the surface of the first oxide layer, and the boundary between the second nitride layer and the first nitride layer is so forming an interface. Thereafter, a second oxide layer is formed on the surface of the second nitride layer completing the process of manufacturing the ONO layer. The second nitride layer and the first nitride layer are used as a floating gate of the NROM, and the interface is used as a deep charge trapping center to improve the charge trapping efficiency, and furthermore, to improve the endurance and reliability of the NROM.
    Type: Application
    Filed: May 10, 2001
    Publication date: November 14, 2002
    Inventors: Kent Kuohua Chang, Uway Tseng
  • Publication number: 20020168869
    Abstract: A substrate is first provided, and a first oxide layer is formed on the surface of the substrate. A rapid thermal nitrifying (RTN) process anneals the first oxide layer and simultaneously nitrifies the surface of the first oxide layer. Then, a low-pressure chemical vapor deposition (LPCVD) process forms a nitride layer on the surface of the first oxide layer. Finally, a second oxide layer is formed on the surface of the nitride layer. The second oxide layer, the nitride layer and the first oxide layer together construct the ONO layer.
    Type: Application
    Filed: May 10, 2001
    Publication date: November 14, 2002
    Inventors: Kent Kuohua Chang, Hsiang-Lan Lung, Fuh-Cheng Jong
  • Publication number: 20020149066
    Abstract: A semiconductor wafer comprises a semiconductor substrate of a first conductive type, a source and a drain of a second conductive type positioned in predetermined areas of the semiconductor substrate, and a channel positioned on the surface of the semiconductor substrate between the source and the drain. The memory device contains a first dielectric layer covering the surface of the channel. A conductive layer covers the surface of the first dielectric layer, the conductive layer containing an insulating region for separating the conductive layer so as to form two isolated conductive regions. A second dielectric layer covers the surface of the conductive layer. A gate covers the surface of the second dielectric layer. Each conductive region is used as a charge trapping layer so as to receive and store electrons injected into the conductive region, thus forming a twin bit cell flash memory device.
    Type: Application
    Filed: March 29, 2001
    Publication date: October 17, 2002
    Inventors: Kent Kuohua Chang, Fuh-Cheng Jong
  • Patent number: 6461949
    Abstract: The present invention provides a method of fabricating an improved gate of a nitride read only memory (NROM) in a semiconductor wafer. A bottom oxide and a silicon nitride layer are first formed on the surface of a silicon substrate in the semiconductor wafer, respectively, followed by injecting a tantalum penta ethoxide (Ta(OC2H5)5), under the condition of 300 mTorr and 200-650° C., to form a tantalum pentaoxide (Ta2O5) layer as a top oxide layer. The top oxide layer, silicon nitride layer and the bottom oxide layer compose an oxide-nitride-oxide (ONO) dielectric structure. Finally, a gate conductor layer is formed on the surface of the ONO structure to complete the fabrication of the NROM of the present invention. The tantalum pentaoxide has a high dielectric constant and is used to reduce the control gate voltage and thermal budget so as to increase the coupling ratio and yield of the semiconductor wafer.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: October 8, 2002
    Assignee: Macronix International Co. Ltd.
    Inventors: Kent Kuohua Chang, Chia-Hsing Chen
  • Publication number: 20020142569
    Abstract: The present invention provides a method of fabricating an improved gate of a nitride read only memory (NROM) in a semiconductor wafer. A bottom oxide and a silicon nitride layer are first formed on the surface of a silicon substrate in the semiconductor wafer, respectively, followed by injecting a tantalum penta ethoxide (Ta(OC2H5)5), under the condition of 300 mTorr and 200-650° C., to form a tantalum pentaoxide (Ta2O5) layer as a top oxide layer. The top oxide layer, silicon nitride layer and the bottom oxide layer compose an oxide-nitride-oxide (ONO) dielectric structure. Finally, a gate conductor layer is formed on the surface of the ONO structure to complete the fabrication of the NROM of the present invention. The tantalum pentaoxide has a high dielectric constant and is used to reduce the control gate voltage and thermal budget so as to increase the coupling ratio and yield of the semiconductor wafer.
    Type: Application
    Filed: March 29, 2001
    Publication date: October 3, 2002
    Inventors: Kent Kuohua Chang, Chia-Hsing Chen
  • Patent number: 6458212
    Abstract: One aspect of the present invention relates to a tetraethylorthosilicate chemical vapor deposition method, involving the steps of forming a film on a substrate using tetraethylorthosilicate in a chemical vapor deposition chamber; and removing tetraethylorthosilicate byproducts from the chemical vapor deposition chamber via a pump system and an exhaust line connected to the chemical vapor deposition chamber, the exhaust line comprising a mesh filter having a conical shape. Another aspect of the present invention relates to an exhaust system for removing tetraethylorthosilicate byproducts from a chemical vapor deposition chamber, containing an exhaust line connected to the chemical vapor deposition chamber, the exhaust line comprising a mesh filter having a conical shape via a pump system; and a pump system connected to the exhaust line for removing tetraethylorthosilicate byproducts from the processing chamber.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: October 1, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Fuodoor Gologhlan, David Chi, Kent Kuohua Chang, Hector Serrato, Jayendra Bhakta
  • Publication number: 20020137289
    Abstract: A process of manufacturing a flash memory device having a tunnel oxide layer with high reliability, low defect and interface trap by using semi-atmospheric pressure chemical vapor deposition (SPACVD) and tetra-ethyl-ortho-silicate (TEOS) reactant. SAPCVD is performed accompanied with a reaction temperature between about 600° C. and about 750° C. and a reaction pressure between about 340 Torr and about 500 Torr to react TEOS and oxygen.
    Type: Application
    Filed: March 22, 2001
    Publication date: September 26, 2002
    Inventor: Kent Kuohua Chang
  • Patent number: 6455890
    Abstract: A structure of fabricating high gate performance for NROM technology. The method at least includes the following steps. First of all, a tunnel oxide layer on the silicon substrate. Then, a amorphous silicon layer on the tunnel oxide layer, and a poly-SiGe layer (a polysilicon layer with doped germanium) on the amorphous silicon layer. Next, an interpoly dielectric layer on the poly-SiGe layer. Finally, a polysilicon layer on the interpoly dielectric layer.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: September 24, 2002
    Assignee: Macronix International Co., Ltd.
    Inventors: Kent Kuohua Chang, Jen-Yuan Chiu
  • Patent number: 6448136
    Abstract: A method of manufacturing flash memory. The method includes using a single wafer consecutive system process. A silicon wafer is placed inside one of the reaction chambers of a chemical vapor deposition station. Tunneling oxide layer, silicon nitride floating gate, silicon oxide layer and control gate are simultaneously formed over wafers inside the station. Breaking the vacuum inside the station and cleaning the wafer are unnecessary between various processing steps.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: September 10, 2002
    Assignee: Macronix International Co., Ltd.
    Inventors: Kent Kuohua Chang, Cheng-Chen Calvin Hsueh
  • Publication number: 20020118566
    Abstract: A method of reading two-bit information in Nitride Read only memory (NROM) cell simultaneously. According to outputted voltage in drain or source of the NROM, it can identify a logical two-bit combination massage of the NROM. The method includes: grounding the source of the NROM; inputting a voltage to the drain of the NROM; inputting a voltage to the gate of the NROM; measuring the outputted current of drain or source; and dividing the outputted current into four different zones, and each zone represents a specific logical two-bit information, which is “0 and 0”, “0 and 1”, “1 and 0”, or “1 and 1”.
    Type: Application
    Filed: February 28, 2001
    Publication date: August 29, 2002
    Inventors: Fuh-Cheng Jong, Kent Kuohua Chang
  • Publication number: 20020119645
    Abstract: A method for preventing electron secondary injection in a pocket implantation process performed on a nitride read only memory (NROM). The NROM has an oxide-nitride-oxide (ONO) layer formed on a silicon substrate. A plurality of bit line masks, arranged in a column, is formed on the surface of the ONO layer. A plurality of N type bit lines is formed in a region of the substrate not covered by the bit line masks. The method starts by performing a pocket implantation process of Indium ions with low energy, high dosage and using an angle nearly parallel to the ONO layer, so as to prevent electron secondary injection. Also, a plurality of P-type ultra-shallow junctions is formed in the region of the substrate not covered by the bit line masks.
    Type: Application
    Filed: August 22, 2001
    Publication date: August 29, 2002
    Inventors: Kent Kuohua Chang, Samuel Cheng-Sheng Pan
  • Publication number: 20020119618
    Abstract: A method for forming a plurality of contact openings on a semiconductor substrate using an etch stop layer is disclosed herein. A semiconductor substrate is provided having a plurality of memory devices and a plurality of isolation regions formed thereon. A silicon oxide layer is formed on the plurality of semiconductor devices, the plurality of isolation regions, and the semiconductor substrate. An etch stop layer is formed on the silicon oxide layer followed by depositing a thick interlevel dielectric layer. A photoresist layer is pattern on the interlevel dielectric layer to define contact regions. A first dry etching process is performed to create a plurality of contact openings with different dimension in the interlevel dielectric layer until exposing portions of the etch stop layer. A second dry etching process is performed to create the plurality of contact openings through the etch stop layer.
    Type: Application
    Filed: February 28, 2001
    Publication date: August 29, 2002
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Uway Tseng, Kent Kuohua Chang, Pei-Hung Chu, Wen-Pin Lu
  • Patent number: 6420237
    Abstract: The present invention provides a twin bit cell flash memory device and its fabricating method. The method is to first form a gate oxide layer on the surface of the silicon substrate followed by forming a polysilicon germanium (Si1−xGex,x=0.05˜1.0) layer on the gate oxide layer. Thereafter, an ion implantation process is performed to form at least one insulating region in the polysilicon germanium layer for separating the polysilicon germanium layer into two isolated conductive regions and forming a twin bit cell structure. Then, a dielectric layer is formed on the polysilicon germanium layer and a photo-etching-process (PEP) is performed to etch portions of the dielectric layer and the polysilicon germanium layer for forming a floating gate of the twin bit cell flash memory. Finally, a control gate is formed over the floating gate.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: July 16, 2002
    Assignee: Macronix International Co. Ltd.
    Inventor: Kent Kuohua Chang
  • Publication number: 20020086548
    Abstract: In fabricating nitride read only memory, a zirconium oxide layer has high dielectric constant and a zirconium oxide layer is replaced conventional tunnel oxide layer. Zirconium oxide layer can increase coupling ratio of gate dielectric layer and reliability for nitride read only memory type flash memory is improved. This invention, a substrate is provided and a zirconium oxide layer is formed on substrate by reactive magnetron sputtering and a silicon nitride layer is sandwiched between a zirconium oxide layer and a silicon oxide layer. Then, an ONO layer (oxide-nitride-oxide layer) is formed. The method is using zirconium oxide as gate dielectric can reduce leakage current, increase drain current, improve subthreshold characteristics, and electron and hole mobilities.
    Type: Application
    Filed: December 14, 2000
    Publication date: July 4, 2002
    Inventor: Kent Kuohua Chang
  • Patent number: 6413840
    Abstract: A method of gettering layer for improving chemical mechanical polishing process in flash-memory production is provided to protect a memory element against baking and keep its reliability by blockading mobile electrons with the gettering layer. Moreover, by taking advantage of the gettering layer, reduction of the thickness of the ILD for increasing the etching margin, the deposition margin, and the remaining margin of oxides are made possible.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: July 2, 2002
    Assignee: Macronix International Co., Ltd.
    Inventors: Uway Tseng, Kent Kuohua Chang, Wen-Pin Lu
  • Patent number: 6410949
    Abstract: The present invention provides a method for monitoring for a second gate over etch in a flash memory device. The method includes providing at least one select transistor stack structure in the core area of the substrate and at least one monitor structure in the monitor area of the substrate; determining a thickness of a select gate layer of the at least one monitor structure; and determining if a second gate over etch occurred upon the thickness of the select gate layer of the at least one monitor structure. The select gate layer of the monitor structure is the same select gate layer of the select transistor stack structure. The select gate thickness of the select transistor stack structure may be determined by measuring the thickness at the monitor structure. This measurement is possible at the monitor area because the monitor structures are placed far enough apart to support measuring instruments.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: June 25, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John JianShi Wang, Kent Kuohua Chang, Hao Fang
  • Publication number: 20020074591
    Abstract: A non-volatile flash memory cell with an application of the DIBL phenomenon is provided and comprises following elements: channel region, control gate, and floating gate. The channel region is located under surface of substrate and between source and drain. The control gate is located over the channel region and insulated to the channel region, and width of the control gate is less than width of the channel region. The floating gate is located between the channel region and the control gate and simultaneously insulated to each other, and a width of the floating gate is less than a width of the channel region and the channel region is not totally covered by the control gate and the floating gate. Besides, the control gate and the floating gate are approximately parallel and a bottom of the control gate is more far from the substrate than a top of the floating gate.
    Type: Application
    Filed: December 20, 2000
    Publication date: June 20, 2002
    Applicant: MACRONIX INTERNATIONAL CO.,LTD.
    Inventors: Fuh-Cheng Jong, Kent Kuohua Chang, Chia-Hsing Chen
  • Publication number: 20020074590
    Abstract: A non-volatile flash memory cell with an asymmetric threshold voltage comprises a channel region, a doping region, a floating gate, and a control gate. The channel region is located in a surface of a substrate and between a source and a drain in the substrate. The doping region is located in one side of the channel region near the source and a plurality of a first dopants and a plurality of a second dopants are doped in the doping region and the substrate with the same conductivity. The control gate is located over the channel region and insulated to the channel region. The floating gate is located between the channel region and the control gate, and is simultaneously insulated to each other. The present flash memory cell still can extend to divide the channel region to a first channel region near the source and a second channel region near the drain without using the doping region. Moreover, a threshold voltage of the first channel region is larger than a threshold voltage of the second channel region.
    Type: Application
    Filed: December 19, 2000
    Publication date: June 20, 2002
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Fu-Cheng Jong, Kent Kuohua Chang, Chia-Hsing Chen
  • Publication number: 20020072217
    Abstract: The method of forming a plurality of contact holes on a semiconductor substrate using multiple-step etching process is disclosed herein. A semiconductor substrate is provided having a plurality of semiconductor devices and a plurality of isolation regions formed thereon. A silicon oxide layer is formed on the plurality of semiconductor devices, the plurality of isolation regions, and the semiconductor substrate. An etching stop layer is formed on the silicon oxide layer followed by depositing an interlevel dielectric layer. A photoresist layer is pattern on the interlevel dielectric layer to define contact regions. A first etching process is performed to create a plurality of contact holes in the interlevel dielectric layer until exposing portions of the etching stop layer. A second etching process is performed to create the plurality of contact holes through the etching stop layer.
    Type: Application
    Filed: December 13, 2000
    Publication date: June 13, 2002
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Uway Tseng, Kent Kuohua Chang, Hung-Yu Chiu, Chi-Yuan Chin