Abstract: A method of manufacturing flash memory. The method includes using a single wafer consecutive system process. A silicon wafer is placed inside one of the reaction chambers of a chemical vapor deposition station. Tunneling oxide layer, silicon nitride floating gate, silicon oxide layer and control gate are simultaneously formed over wafers inside the station. Breaking the vacuum inside the station and cleaning the wafer are unnecessary between various processing steps.

Abstract: A non-volatile flash memory cell with a short floating gate comprises: a channel region which is located in a surface of a substrate and between a source and a drain; a control gate which is located over the channel region and simultaneously insulated to the channel region; and a floating gate which is located between the channel region and the control gate, and simultaneously insulated to each other, wherein a width of the floating gate is less than the control gate and the channel region. Besides, the floating gate and the control gate are approximately parallel, and a bottom of the control gate is more far from the substrate than a top of the floating gate. Obviously, the characteristic of the present invention is the channel region can divide to two parts which one is under and another is not under the floating gate. However, even the over erase causes the short of the channel region which is under the floating gate, the channel region which is not under the floating gate still is not conducted.

Abstract: A method for fabricating a nitride read-only memory (NROM). A gate structure comprising an oxide/nitride/oxide composite layer and a gate conductive layer is formed on a substrate. A source/drain region is formed in the substrate beside the gate structure. A silicon oxide spacer is formed on the side-wall of the gate structure and then a silicon nitride spacer is formed on the side-wall of the silicon oxide spacer. The surface of the substrate is cleaned and a metal silicide layer is further formed on the source/drain region. Since the silicon nitride spacer is capable of protecting the silicon oxide spacer from thinning during the cleaning step, a junction leakage can be prevented. Meanwhile, the parasitic capacitance between the gate and the source/drain region is lower by adopting the silicon oxide spacer, so that the performance of the device can be improved.

Abstract: In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second polysilicon layer over the insulating layer; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF6 and SiH2Cl2; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

Abstract: The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device.

Abstract: A semiconductor process for fabricating NAND type flash memory devices in a first embodiment includes step which can be performed on a production line which manufactures NOR type flash memory products. A NAND flash memory fabrication process according to a second embodiment simplifies the process and uses fewer masks, thus reducing costs and errors to produce higher yields.

Abstract: In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide by chemical vapor deposition using a silicon containing gas and a mixture of a phosphorus containing gas and a carrier gas, the first polysilicon layer having a thickness from about 800 Å to about 1,000 Å; forming an insulating layer over the first polysilicon layer, the insulating layer comprising a first oxide layer over the first polysilicon layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second polysilicon layer over the insulating layer; forming a tungsten silicide layer over the second polysilicon layer by chemical vapor deposition using WF6 and SiH2Cl2; etching at least the first polysilicon layer, the second polysilicon layer, the insulating layer, and the tungsten silicide layer thereby defining at least one stacked gate

Abstract: A method for forming a nonvolatile memory with optimum bias condition is disclosed. Initially, an ONO structure is formed on the substrate wherein the ONO structure has a first oxide layer, a nitride layer and a second oxide layer. Afterwards, a plurality of openings is formed on the ONO structure and a portion of substrate is exposed. An optimum condition of a nonvolatile memory cell having a threshold voltage region wherein the threshold voltage region can be optimum by adjusting a lateral electric field between a drain and a gate to transfer a plurality of electrons into the ONO structure. Thereafter, an implant process is performed to form a plurality of bit lines on substrate. An oxide layer is formed on bit lines to create a bit lines oxide layer. Finally, a polysilicon is formed on bit lines oxide layer and the ONO structure to produce the nonvolatile memory cell.

Abstract: In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising an oxide layer over the first polysilicon layer, and a tantalum pentoxide layer over the oxide layer, wherein the tantalum pentoxide layer is made by chemical vapor deposition at a temperature from about 200° C. to about 650° C. using an organic tantalum compound and an oxygen compound, and heating in an N2O atmosphere at a temperature from about 700° C. to about 875° C.; forming a second polysilicon layer over the insulating layer; etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

Abstract: The present invention provides a method for monitoring for a second gate over etch in a flash memory device. The method includes providing at least one select transistor stack structure in the core area of the substrate and at least one monitor structure in the monitor area of the substrate; determining a thickness of a select gate layer of the at least one monitor structure; and determining if a second gate over etch occurred upon the thickness of the select gate layer of the at least one monitor structure. The select gate layer of the monitor structure is the same select gate layer of the select transistor stack structure. The select gate thickness of the select transistor stack structure may be determined by measuring the thickness at the monitor structure. This measurement is possible at the monitor area because the monitor structures are placed far enough apart to support measuring instruments.

Abstract: A random access memory cell. The RAM cell includes a first transistor and a second transistor. A control gate of the first transistor is coupled to a control signal line. A data read terminal of the first transistor is coupled to a data read line. An earth terminal of the first transistor is connected to a ground. A floating gate terminal of the first transistor is located between a portion of a substrate and a portion of the control gate. A control gate of the second transistor is also coupled to the control signal line. The data write terminal of the second transistor is a data write line. A data transmission terminal of the second transistor is coupled to the floating gate of the first transistor. To write data into the RAM cell, a write control voltage is applied to the control signal line. Similarly, to read data from the RAM cell, a read control voltage is applied to the control signal line. The write control voltage is greater than the read control voltage.

Abstract: In one embodiment, the present invention relates to a method of forming a flash memory cell, involving the steps of forming a tunnel oxide on a substrate; forming a first polysilicon layer over the tunnel oxide; forming an insulating layer over the first polysilicon layer, the insulating layer comprising an oxide layer over the first polysilicon layer, and a tantalum pentoxide layer over the oxide layer, wherein the tantalum pentoxide layer is made by chemical vapor deposition at a temperature from about 200° C. to about 650° C. using an organic tantalum compound and an oxygen compound, and heating in an N2O atmosphere at a temperature from about 700° C. to about 875° C.; forming a second polysilicon layer over the insulating layer; etching at least the first polysilicon layer, the second polysilicon layer and the insulating layer, thereby defining at least one stacked gate structure; and forming a source region and a drain region in the substrate, thereby forming at least one memory cell.

Abstract: The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device.

Abstract: Polystringers that cause NAND-type memory core cells to malfunction are covered by ONO fence material. ONO fence is removed so that polystringers may then be removed more readily. A SiON layer, tungsten silicide layer, second polysilicon layer, ONO dielectric, and first polysilicon layer are successively removed from between NAND-type flash memory core cells leaving ONO fence that shields some first polysilicon layer material from removal. The device is next exposed to an hydrogen-fluoride solution to remove oxide-based materials, particularly ONO fence. Thereafter, the polystringers are exposed and may thus be removed more readily.

Abstract: The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device.

Abstract: The present invention provides a method for providing an interconnect in a flash memory device. A first embodiment includes forming at least one contact hole in a peripheral area of the device; bombarding a bottom of the at least one contact hole with ions, where the ions break down undesired oxide residing at the bottom of the at least one contact hole; depositing a barrier metal layer into the at least one contact hole, where the barrier metal layer breaks down remaining undesired oxide at the bottom of the at least one contact hole, and where bombarding with the ions and the depositing of the barrier metal layer minimize an undesired widening of the at least one contact hole; and depositing a contact material into the at least one contact hole. With the first embodiment, both the ions and the titanium break down the undesired oxide while neither breaks down the desired oxide at the sides of the contact hole to a significant degree.

Abstract: The present invention provides a method for monitoring for a second gate over etch in a flash memory device. The method includes providing at least one select transistor stack structure in the core area of the substrate and at least one monitor structure in the monitor area of the substrate; determining a thickness of a select gate layer of the at least one monitor structure; and determining if a second gate over etch occurred upon the thickness of the select gate layer of the at least one monitor structure. The select gate layer of the monitor structure is the same select gate layer of the select transistor stack structure. The select gate thickness of the select transistor stack structure may be determined by measuring the thickness at the monitor structure. This measurement is possible at the monitor area because the monitor structures are placed far enough apart to support measuring instruments.

Abstract: In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell

Abstract: In one embodiment, the present invention relates to a method of cleaning a low pressure chemical vapor deposition apparatus having TEOS material build-up therein involving contacting the low pressure chemical vapor deposition apparatus with a composition containing at least one lower alcohol. In another embodiment, the present invention relates to a system for cleaning a low pressure chemical vapor deposition apparatus having TEOS material build-up therein, containing a supply of a composition comprising at least one lower alcohol; an injection port for introducing the composition comprising at least one lower alcohol into the low pressure chemical vapor deposition apparatus; and a pump/vacuum system for removing crystallized TEOS material build-up from the low pressure chemical vapor deposition apparatus.

Abstract: The present invention provides a method and a NAND-type flash memory device. The method includes forming a select gate oxide layer in a select transistor area of a substrate and a tunnel oxide layer in a memory cell area of the substrate; forming a doped amorphous silicon layer on the select gate oxide layer and the tunnel oxide layer, the doped amorphous silicon layer having a dopant level which simultaneously avoids a select transistor word line high resistance problem and a charge gain/charge loss problem; forming an insulating layer on the doped amorphous silicon layer; forming a control gate layer on the insulating layer; and etching at least the doped amorphous silicon layer, the insulating layer, and the control gate layer to form at least one memory cell stack structure and at least one select transistor stack structure.