Patents by Inventor Keon Soo Shim

Keon Soo Shim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6697288
    Abstract: A bit line voltage regulation circuit achieves uniform program features and precise cell distribution by providing a high voltage to a bit line regardless of a cell state. For this purpose, the regulation circuit includes a boosting unit for generating the high voltage, a switching unit, connected between the boosting unit and the bit line of a memory cell array, for transferring the high voltage to the bit line and an amplifying unit, for detecting a voltage drop at a detection node on the bit line caused by resistance on the bit line, amplifying the detected voltage drop to produce an amplified voltage driving the switching unit.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: February 24, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ki-Seog Kim, Keun-Woo Lee, Seoung-Ouk Choi, Keon-Soo Shim
  • Publication number: 20030124800
    Abstract: The present invention relates to a method of forming a floating gate in a flash memory device. Upon formation of a device isolation film, a space of a lower polysilicon layer for a floating gate is defined, a bird's beak is formed on an internal surface of a trench by subsequent well sacrificial oxidization process and well oxidization process and an upper polysilicon layer for a floating gate is then formed, so that the space of the floating gate is formed. Therefore, the present invention can reduce the cost since a mask process is not required compared to an existing stepper method and the process cost since a planarization process using chemical mechanical polishing process (CMP) is not required compared to the self-aligned floating mode.
    Type: Application
    Filed: November 4, 2002
    Publication date: July 3, 2003
    Inventors: Sung Kee Park, Ki Seog Kim, Keun Woo Lee, Keon Soo Shim
  • Patent number: 6455374
    Abstract: The present invention relates to a method of manufacturing a flash memory device. According to the present invention, a dielectric film is formed and an amorphous silicon layer is then formed to mitigate a topology generated by patterning of a first polysilicon layer in a cell region. The amorphous silicon layer serves as a protection layer of the dielectric film in the cell region when a gate oxide film in a peripheral circuit region is formed. Therefore, the present invention can not only improve the resistance of a word line in the cell region but also improve the film quality of the dielectric film and the gate oxide film in the peripheral circuit region.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: September 24, 2002
    Assignee: Hynix Semiconductor Inc.
    Inventors: Keun Woo Lee, Bong Kil Kim, Ki Jun Kim, Keon Soo Shim
  • Publication number: 20020089375
    Abstract: A bit line voltage regulation circuit achieves uniform program features and precise cell distribution by providing a high voltage to a bit line regardless of a cell state. For this purpose, the regulation circuit includes a boosting unit for generating the high voltage, a switching unit, connected between the boosting unit and the bit line of a memory cell array, for transferring the high voltage to the bit line and an amplifying unit, for detecting a voltage drop at a detection node on the bit line caused by resistance on the bit line, amplifying the detected voltage drop to produce an amplified voltage driving the switching unit.
    Type: Application
    Filed: December 28, 2001
    Publication date: July 11, 2002
    Inventors: Ki-Seog Kim, Keun-Woo Lee, Seoung-Ouk Choi, Keon-Soo Shim
  • Patent number: 6304484
    Abstract: There is disclosed a multi-bit flash memory cell and programming method using the same. In order to solve the problems that the size of a cell per unit is increased, reliability of a device is degraded due to a high operating voltage and a circuit necessary for driving the cell becomes complicated, the multi-bit flash memory cell and programming method using the same according to the present invention stores information of various states, by interchangeably programs a drain and a source in a cell array of virtual ground type, in a structure in which that two types of cells look like connected serially by doping a floating gate in a flash memory cell with two regions of a N type and a P to type.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: October 16, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Jin Shin, Sang Hoan Chang, Seoung Ouk Choi, Keon Soo Shim