Patents by Inventor Kerry A. Ilgenstein
Kerry A. Ilgenstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11056160Abstract: As disclosed herein, a non-volatile memory circuit includes an array of memory cells. The non-volatile memory circuit also includes circuitry for performing a hard write to selective bits of addressed cells simultaneously with a normal write to the other bits of the addressed cells during a write operation to the addressed cells.Type: GrantFiled: October 22, 2019Date of Patent: July 6, 2021Assignee: NXP USA, INC.Inventors: Richard Eguchi, Jon Scott Choy, Anirban Roy, Jacob Williams, Kerry Ilgenstein
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Publication number: 20210118475Abstract: As disclosed herein, a non-volatile memory circuit includes an array of memory cells. The non-volatile memory circuit also includes circuitry for performing a hard write to selective bits of addressed cells simultaneously with a normal write to the other bits of the addressed cells during a write operation to the addressed cells.Type: ApplicationFiled: October 22, 2019Publication date: April 22, 2021Inventors: Richard Eguchi, Jon Scott Choy, Anirban Roy, Jacob Williams, Kerry Ilgenstein
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Patent number: 9300296Abstract: A level shifting circuit that includes a level shifter and a circuit stage. The circuit stage includes a pair of diodes circuits. The circuit stage includes a first output node and a second output node. The first output node is coupled via a current path to a first output of the level shifter and the second output node is coupled to via a current path to a second output of the level shifter. One of the diodes is coupled to the first output node and a power supply terminal. The other diode is coupled to the second output node and the power supply terminal.Type: GrantFiled: December 18, 2013Date of Patent: March 29, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Kerry A. Ilgenstein, Gilles J. Muller
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Publication number: 20150171866Abstract: A level shifting circuit that includes a level shifter and a circuit stage. The circuit stage includes a pair of diodes circuits. The circuit stage includes a first output node and a second output node. The first output node is coupled via a current path to a first output of the level shifter and the second output node is coupled to via a current path to a second output of the level shifter. One of the diodes is coupled to the first output node and a power supply terminal. The other diode is coupled to the second output node and the power supply terminal.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Kerry A. Ilgenstein, Gilles J. Muller
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Patent number: 8823445Abstract: A power control circuit includes a plurality of transistors coupled between a power supply node and a gated power supply node, wherein the gate electrode of a first transistor of the plurality of transistors is coupled to receive a power control signal, wherein, in response to assertion of the power control signal, the first transistor is placed into a conductive state; a first voltage comparator, wherein, in response to assertion of the power control signal, places a second transistor of the plurality of transistors in a conductive state when a voltage on the gated voltage supply node reaches a first reference voltage; and a second voltage comparator, wherein, in response to assertion of the power control signal, places a third transistor of the plurality of transistors in a conductive state when the voltage on the gated voltage supply node reaches a second reference voltage different from the first reference voltage.Type: GrantFiled: November 29, 2012Date of Patent: September 2, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Jon S. Choy, Kerry A. Ilgenstein
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Publication number: 20140145699Abstract: A power control circuit includes a plurality of transistors coupled between a power supply node and a gated power supply node, wherein the gate electrode of a first transistor of the plurality of transistors is coupled to receive a power control signal, wherein, in response to assertion of the power control signal, the first transistor is placed into a conductive state; a first voltage comparator, wherein, in response to assertion of the power control signal, places a second transistor of the plurality of transistors in a conductive state when a voltage on the gated voltage supply node reaches a first reference voltage; and a second voltage comparator, wherein, in response to assertion of the power control signal, places a third transistor of the plurality of transistors in a conductive state when the voltage on the gated voltage supply node reaches a second reference voltage different from the first reference voltage.Type: ApplicationFiled: November 29, 2012Publication date: May 29, 2014Inventors: Jon S. Choy, Kerry A. Ilgenstein
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Patent number: 7301182Abstract: In one embodiment, a circuit may be formed by forming at least one bent-gate output stage transistor and at least one bent-gate input stage transistor. The bent-gate output stage transistor may be electrically isolated from an input to the bent-gate input stage transistor by forming at least one bent-gate grounded-gate transistor between the bent-gate output stage transistor and the input to the bent-gate input stage transistor.Type: GrantFiled: September 13, 2005Date of Patent: November 27, 2007Assignee: Lattice Semiconductor CorporationInventors: Larry Metzger, Kerry Ilgenstein, Sunil Mehta
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Patent number: 7242053Abstract: In one embodiment, an EEPROM device having voltage limiting charge pumping circuitry includes charge-pumping circuitry that limits the voltage supplied to the high voltage transistors to levels below the breakdown field of the tunnel oxide layer. The EEPROM device includes a substrate having a programming region, a tunnel region, a sensing region, and a low voltage region. A first oxide layer having a first thickness overlies the tunnel region and the sensing region. A second oxide layer having a second thickness overlies the low voltage region. The first oxide thickness is greater than the second oxide thickness. A charge pumping circuit is coupled to the programming region and to the tunnel region. The charge pumping circuit impresses a voltage level across the first oxide layer that is below the field breakdown voltage of first oxide layer.Type: GrantFiled: January 14, 2005Date of Patent: July 10, 2007Assignee: Lattice Semiconductor CorporationInventors: Sunil D. Mehta, Kerry Ilgenstein
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Publication number: 20050213271Abstract: Systems and methods disclosed provide electrostatic discharge protection. For example, in accordance with an embodiment of the present invention, a circuit is disclosed having a diode string and a transistor in a cascode configuration that provides electrostatic discharge (ESD) protection and can operate in a mixed voltage environment.Type: ApplicationFiled: March 24, 2004Publication date: September 29, 2005Inventors: Nui Chong, Aaron Rogers, Kerry Ilgenstein
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Publication number: 20050093577Abstract: Multiplexer circuits are disclosed, such as for example for programmable logic devices. As an example of one embodiment, a multiplexer circuit is disclosed having a default state and a state-locking latch.Type: ApplicationFiled: November 4, 2003Publication date: May 5, 2005Inventors: Liem Nguyen, Xiaojie He, Brian Gaide, Kerry Ilgenstein, Sajitha Wijesuriya, Claudia Stanley, Aaron Rogers, Zheng Chen
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Patent number: 6846714Abstract: An EEPROM device having voltage limiting charge pumping circuitry includes charge pumping circuitry that limits the voltage supplied to the high voltage transistors to levels below the breakdown field of the tunnel oxide layer. The EEPROM device includes a substrate having a programming region, a tunnel region, a sensing region, and a low voltage region. A first oxide layer having a first thickness overlies the tunnel region and the sensing region. A second oxide layer having a second thickness overlies the low voltage region. The first oxide thickness is greater than the second oxide thickness. A charge pumping circuit is coupled to the programming region and to the tunnel region. The charge pumping circuit impresses a voltage level across the first oxide layer that is below the field breakdown voltage of first oxide layer. A process for fabricating the device is also provided.Type: GrantFiled: October 3, 2002Date of Patent: January 25, 2005Assignee: Lattice Semiconductor CorporationInventors: Sunil D. Mehta, Kerry Ilgenstein
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Patent number: 6348813Abstract: An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications.Type: GrantFiled: November 22, 2000Date of Patent: February 19, 2002Assignee: Lattice Semiconductor CorporationInventors: Om P. Agrawal, Claudia A. Stanley, Xiaojie (Warren) He, Larry R. Metzger, Robert A. Simon, Kerry A. Ilgenstein
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Patent number: 6184713Abstract: An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications.Type: GrantFiled: June 6, 1999Date of Patent: February 6, 2001Assignee: Lattice Semiconductor CorporationInventors: Om P. Agrawal, Claudia A. Stanley, Xiaojie (Warren) He, Larry R. Metzger, Robert A. Simon, Kerry A. Ilgenstein
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Patent number: 6150841Abstract: An improved CPLD includes a plurality of macrocell modules (MM's) where each MM can receive a relatively large number of independent inputs (at least 80) and can generate at least 5 different product term signals (PT's) therefrom. All 5 PT's may be used for generating a local sum-of-products (SoP). Any of the 5 PT's may be stolen (steered-away) to instead provide a local control for its macrocell module. Each module includes a local SoS-producing gate that can produce a sums-of-sums signal (SoS) that represents a Boolean sum of one or more of the local SoP signal, of SoP signals of neighboring macrocell modules, and of SoS signals of neighboring macrocell modules. Simple allocation and super-allocation may be used to produce sums-of-sums signals of relatively large, one-pass function depth, such as 160PT's in one pass.Type: GrantFiled: June 6, 1999Date of Patent: November 21, 2000Assignee: Lattice Semiconductor CorporationInventors: Om P. Agrawal, Claudia A. Stanley, Xiaojie (Warren) He, Chong M. Lee, Robert M. Balzli, Jr., Larry R. Metzger, Kerry A. Ilgenstein
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Patent number: 6028446Abstract: A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell also includes an I/O cell and an input macrocell. In addition the PLD cell includes a sub-bank of a programmable output switch matrix bank and a sub-bank of a programmable input switch matrix bank. Each programmable logic block cell includes a multiplicity of product terms. At least one product term in the cluster is programmably available to the cluster. When the product term is disconnected from the cluster, the product term is used for control of the polarity of the logic macrocell output signal or asynchronous functions. Thus, the programmably connectable product term can be used for either synchronous or asynchronous operations. If the programmably connectable and disconnectable product term is connected to the product term cluster, the programmable logic block cell is used for synchronous operations.Type: GrantFiled: July 17, 1998Date of Patent: February 22, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Om P. Agrawal, Kerry A. Ilgenstein
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Patent number: 5869981Abstract: Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell.Type: GrantFiled: June 6, 1995Date of Patent: February 9, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Om P. Agrawal, George H. Landers, Nicholas A. Schmitz, Jerry D. Moench, Kerry A. Ilgenstein
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Patent number: 5811986Abstract: A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell also includes an I/O cell and an input macrocell. In addition the PLD cell includes a sub-bank of a programmable output switch matrix bank and a sub-bank of a programmable input switch matrix bank. Each programmable logic block cell includes a multiplicity of product terms. At least one product term in the cluster is programmably available to the cluster. When the product term is disconnected from the cluster, the product term is used for control of the polarity of the logic macrocell output signal or asynchronous functions. Thus, the programmably connectable product term can be used for either synchronous or asynchronous operations. If the programmably connectable and disconnectable product term is connected to the product term cluster, the programmable logic block cell is used for synchronous operations.Type: GrantFiled: June 6, 1995Date of Patent: September 22, 1998Assignee: Advanced Micro Devices, Inc.Inventors: Om P. Agrawal, Kerry A. Ilgenstein
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Patent number: 5489857Abstract: A programmable logic device (PLD) cell is used to construct a high density high performance programmable logic device (PLD). The PLD cell includes two programmable logic block cells. The PLD cell also includes an I/O cell and an input macrocell. In addition the PLD cell includes a sub-bank of a programmable output switch matrix bank and a sub-bank of a programmable input switch matrix bank. Each programmable logic block cell includes a multiplicity of product terms. At least one product term in the cluster is programmably available to the cluster. When the product term is disconnected from the cluster, the product term is used for control of the polarity of the logic macrocell output signal or asynchronous functions. Thus, the programmably connectable product term can be used for either synchronous or asynchronous operations. If the programmably connectable and disconnectable product term is connected to the product term cluster, the programmable logic block cell is used for synchronous operations.Type: GrantFiled: August 3, 1992Date of Patent: February 6, 1996Assignee: Advanced Micro Devices, Inc.Inventors: Om P. Agrawal, Kerry A. Ilgenstein
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Patent number: 5485104Abstract: Each programmable logic device in at least two families of high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programmable logic blocks. Each programmable logic block includes programmable logic macrocells, programmable input/output macrocells, a logic allocator and a programmable product term array. The programmable switch matrix provides centralized global routing with a fixed path independent delay and decouples the logic macrocells from the product term array. The logic allocator decouples the product term array from the logic macrocells, and the I/O macrocells decouple the logic macrocells from the package I/O pins. The logic allocator steers product terms from the product term array to selected logic macrocells so that no product terms are permanently allocated to a specific logic macrocell.Type: GrantFiled: January 18, 1995Date of Patent: January 16, 1996Assignee: Advanced Micro Devices, Inc.Inventors: Om P. Agrawal, Jerry D. Moench, Kerry A. Ilgenstein
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Patent number: 5457409Abstract: The programmable logic device (PLD) of this invention includes two or more programmable logic blocks interconnected by a programmable switch matrix that includes a programmable input switch matrix (input switch matrix) and a programmable centralized switch matrix (centralized switch matrix). Each programmable logic block receives input signals only from the centralized switch matrix. The output signals from a programmable logic block are coupled to a plurality of input/output (I/O) pins by an output switch matrix. The output signals from the programmable logic block are also fed directly to the programmable input switch matrix. In addition, an input macrocell couples the signal on an I/O pin driving the input macrocell, i.e., the associated I/O pin, to the programmable input switch matrix. Each programmable logic block includes a programmable logic array, a programmable logic allocator, and programmable logic macrocells.Type: GrantFiled: August 3, 1992Date of Patent: October 10, 1995Assignee: Advanced Micro Devices, Inc.Inventors: Om P. Agrawal, Jerry D. Moench, Kerry A. Ilgenstein