Patents by Inventor Keum-hee Lee

Keum-hee Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200358040
    Abstract: A method of manufacturing a thin film transistor includes: forming an active pattern on a substrate; forming an insulating layer and a gate electrode layer on the active pattern in order; forming a photoresist pattern on the gate electrode layer; forming a preliminary gate electrode by wet etching the gate electrode layer using the photoresist pattern; forming an insulating pattern by dry etching the insulating layer using the photoresist pattern and the preliminary gate electrode; and forming a gate electrode by wet etching a side surface of the preliminary gate electrode using the photoresist pattern.
    Type: Application
    Filed: March 27, 2020
    Publication date: November 12, 2020
    Inventors: Keum Hee LEE, Joongeol KIM, Kap Soo YOON, Woo Geun LEE, Seung-Ha CHOI, Jiyun HONG
  • Patent number: 10310340
    Abstract: A Liquid crystal display device and manufacturing method thereof are provided. According to an exemplary embodiment of the present disclosure, an LCD device includes: a first substrate including a display area and a non-display area disposed outside of the display area; a gate electrode disposed on the first substrate and including a first-layer gate electrode and a second-layer gate electrode disposed on the first-layer gate electrode; a pixel electrode disposed on the same layer as the first-layer gate electrode; a source electrode and a drain electrode disposed on the gate electrode to be spaced from each other; and a contact connecting the drain electrode and the pixel electrode and including a first-layer contact, which is disposed on the same layer as the pixel electrode, and a second-layer contact, which is disposed on the first-layer contact.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: June 4, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Keum Hee Lee, Man Jin Kim, Yu Jun Kim, Chang Yeol Lee, Su Jung Jung, Ji Young Jeong
  • Patent number: 10032803
    Abstract: A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal suicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: July 24, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Zhu Xun, Jae Woo Park, Jae Won Song, Keum Hee Lee, June Whan Choi
  • Publication number: 20170205656
    Abstract: A Liquid crystal display device and manufacturing method thereof are provided. According to an exemplary embodiment of the present disclosure, an LCD device includes: a first substrate including a display area and a non-display area disposed outside of the display area; a gate electrode disposed on the first substrate and including a first-layer gate electrode and a second-layer gate electrode disposed on the first-layer gate electrode; a pixel electrode disposed on the same layer as the first-layer gate electrode; a source electrode and a drain electrode disposed on the gate electrode to be spaced from each other; and a contact connecting the drain electrode and the pixel electrode and including a first-layer contact, which is disposed on the same layer as the pixel electrode, and a second-layer contact, which is disposed on the first-layer contact.
    Type: Application
    Filed: January 4, 2017
    Publication date: July 20, 2017
    Inventors: Keum Hee LEE, Man Jin KIM, Yu Jun KIM, Chang Yeol LEE, Su Jung JUNG, Ji Young JEONG
  • Patent number: 9691790
    Abstract: A display substrate includes a gate metal pattern including a gate line on a base substrate and extending in a first direction, and a gate electrode electrically connected with the gate line, a data metal pattern on the gate metal pattern and including a data line extending in a second direction crossing the first direction, a source electrode electrically connected with the gate line and a drain electrode spaced apart from the source electrode, a first electrode pattern on the data metal pattern, a low-resistance electrode pattern on the first electrode pattern and entirely overlapping with the gate metal pattern and the data metal pattern and a second electrode pattern overlapping with the first electrode pattern.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 27, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Xinxing Li, Man-Jin Kim, Jong-Kyun Park, Keum-Hee Lee, Gi-Jung Lee, Chan-Young Lim
  • Publication number: 20170053940
    Abstract: A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal suicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.
    Type: Application
    Filed: November 4, 2016
    Publication date: February 23, 2017
    Inventors: ZHU XUN, JAE WOO PARK, JAE WON SONG, KEUM HEE LEE, JUNE WHAN CHOI
  • Patent number: 9515093
    Abstract: A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal silicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: December 6, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Zhu Xun, Jae Woo Park, Jae Won Song, Keum Hee Lee, June Whan Choi
  • Publication number: 20160216584
    Abstract: A liquid crystal display and a manufacturing method thereof are disclosed, whereby a common electrode having a planar shape is formed directly on a common voltage line, and a semiconductor layer is formed on the common electrode and a gate line. The common electrode and a pixel electrode are formed on one substrate, with the common electrode being formed directly on the common voltage line. Accordingly, the costs of manufacturing the liquid crystal display may be reduced, and signal delay of a common voltage can be prevented.
    Type: Application
    Filed: July 21, 2015
    Publication date: July 28, 2016
    Inventors: Keum Hee LEE, Young Joo CHOI
  • Publication number: 20160126255
    Abstract: A display substrate includes a gate metal pattern including a gate line on a base substrate and extending in a first direction, and a gate electrode electrically connected with the gate line, a data metal pattern on the gate metal pattern and including a data line extending in a second direction crossing the first direction, a source electrode electrically connected with the gate line and a drain electrode spaced apart from the source electrode, a first electrode pattern on the data metal pattern, a low-resistance electrode pattern on the first electrode pattern and entirely overlapping with the gate metal pattern and the data metal pattern and a second electrode pattern overlapping with the first electrode pattern.
    Type: Application
    Filed: March 27, 2015
    Publication date: May 5, 2016
    Inventors: Xinxing Li, Man-Jin Kim, Jong-Kyun Park, Keum-Hee Lee, Gi-Jung Lee, Chan-Young Lim
  • Publication number: 20150200212
    Abstract: A thin film transistor array panel is provided as follows. A gate electrode is disposed on a substrate. A semiconductor layer is disposed on the gate electrode. A gate insulating layer is disposed between the gate electrode and the semiconductor layer. A source electrode is disposed on a first side of the semiconductor layer, having a first lateral surface. A drain electrode is disposed on a second side of the semiconductor layer, having a second lateral surface. The first and second lateral surfaces define a spacing which overlaps the gate electrode. A metal silicide layer is disposed on the first and second lateral surfaces. A passivation layer is disposed on the metal silicide layer, the source electrode and the drain electrode. The passivation layer is not in contact with the first and second lateral surfaces.
    Type: Application
    Filed: August 22, 2014
    Publication date: July 16, 2015
    Inventors: Zhu XUN, Jae Woo PARK, Jae Won SONG, Keum Hee LEE, June Whan CHOI
  • Patent number: 6270583
    Abstract: A compound semiconductor wet thermal oxidation apparatus includes a chamber unit having an inside tube containing water and supporting a specimen and an outside tube encompassing the inside tube forming a seal, and a heating unit having a furnace for heating the specimen and the water.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: August 7, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-doo Choi, Jeong-kwan Lee, Keum-hee Lee