Patents by Inventor Keun-hyuk Lee
Keun-hyuk Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9130065Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.Type: GrantFiled: May 28, 2014Date of Patent: September 8, 2015Assignee: Fairchild Korea Semiconductor, LtdInventors: Seungwon Im, O-Seob Jeon, Joon-seo Son, Keun-hyuk Lee, Yun-hwa Choi
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Publication number: 20140273349Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.Type: ApplicationFiled: May 28, 2014Publication date: September 18, 2014Applicant: Fairchild Korea Semiconductor, Ltd.Inventors: Seung-won Lim, O-Seob Jeon, Joon-seo Son, Keun-hyuk Lee, Yun-hwa Choi
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Patent number: 8350369Abstract: Provided is a high power semiconductor package including: an insulation substrate having first and second surfaces opposite to each other; an interconnection patterns formed on the first surface of the insulation substrate, the interconnection patterns including a plurality of first dimples; a power control semiconductor chip mounted on the first surface of the insulation substrate, the power control semiconductor chip electrically connected with the interconnection patterns; and an encapsulation member encapsulating the insulation substrate, the interconnection patterns, and the power control semiconductor chip and exposing at least a portion of the second surface of the insulation substrate.Type: GrantFiled: January 4, 2008Date of Patent: January 8, 2013Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Keun-hyuk Lee, Seung-won Lim, Sung-min Park, Taek-keun Lee
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Patent number: 8258622Abstract: Provided are a power device package coupled to a heat sink using a bolt and a semiconductor package mold for fabricating the same. The power device package includes: a substrate; at least one power device mounted on the substrate; a mold member sealing the substrate and the power device; and at least one bushing member fixed to the mold member to provide a through hole for a bolt member for coupling a heat sink to the mold member.Type: GrantFiled: January 29, 2008Date of Patent: September 4, 2012Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Keun-hyuk Lee, Seung-won Lim, Sung-min Park
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Patent number: 8125080Abstract: Provided are semiconductor power module packages, which are structurally simplified by bonding electrodes onto substrates, and methods of fabricating the same. An exemplary package includes a substrate and semiconductor chips disposed on a top surface of the substrate. Electrodes are bonded to the top surface of the substrate and electrically coupled to the semiconductor chips. Parts of the semiconductor chips are electrically coupled to parts of the electrodes by interconnection lines. An encapsulation unit covers the semiconductor chips, the electrodes, and the interconnection lines and exposes at least top surfaces of the electrodes.Type: GrantFiled: November 4, 2008Date of Patent: February 28, 2012Assignee: Fairchild Korea Semiconductor Ltd.Inventor: Keun-hyuk Lee
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Patent number: 8013431Abstract: Provided are a semiconductor power module package and a method of fabricating the same. The semiconductor power module package includes a substrate, semiconductor chips arranged on a top surface of the substrate, and a temperature sensor mounted on a top surface of at least one of the semiconductor chips. The semiconductor chips and the temperature sensor are electrically connected to each other through leads. A sealing material covers the top surface of the substrate, the semiconductor chips, and the temperature sensor except for portions of the leads and a bottom surface of the substrate. The temperature sensor may include a thermistor, and the thermistor may include first and second electrode terminals connected to corresponding leads of the leads. A first wiring pattern may be in contact with the first electrode terminal, and a second wiring pattern may be in contact with the second electrode terminal.Type: GrantFiled: December 7, 2010Date of Patent: September 6, 2011Assignee: Fairchild Korea Semiconductor Ltd.Inventor: Keun-hyuk Lee
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Patent number: 7986531Abstract: Provided are a power system module allowing a user's requirements to be easily met, and having economic practicality and high integration, and a manufacturing method thereof. The power system module includes a plastic case, a molding type power module package, a control circuit board, and at least one external terminal. The plastic case defines a bottom and a side wall. The molding type power module package is fixed to the bottom of the plastic case and includes at least a power device therein. The control circuit board is fixed to the side wall of the plastic case, includes at least a control device mounted thereon which is electrically connected to the power module package. The external terminal protrudes to outside the plastic case and is electrically connected to the control circuit board.Type: GrantFiled: March 11, 2010Date of Patent: July 26, 2011Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Keun-hyuk Lee, Seung-won Lim, Seung-han Paek, Sung-min Park
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Patent number: 7951645Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.Type: GrantFiled: February 9, 2010Date of Patent: May 31, 2011Assignee: Fairchild Korea Semiconductor, LtdInventors: Keun-hyuk Lee, O-seob Jeon, Seung-won Lim
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Publication number: 20110073984Abstract: Provided are a semiconductor power module package and a method of fabricating the same. The semiconductor power module package includes a substrate, semiconductor chips arranged on a top surface of the substrate, and a temperature sensor mounted on a top surface of at least one of the semiconductor chips. The semiconductor chips and the temperature sensor are electrically connected to each other through leads. A sealing material covers the top surface of the substrate, the semiconductor chips, and the temperature sensor except for portions of the leads and a bottom surface of the substrate. The temperature sensor may include a thermistor, and the thermistor may include first and second electrode terminals connected to corresponding leads of the leads. A first wiring pattern may be in contact with the first electrode terminal, and a second wiring pattern may be in contact with the second electrode terminal.Type: ApplicationFiled: December 7, 2010Publication date: March 31, 2011Applicant: Fairchild Korea Semiconductor Ltd.Inventor: Keun-hyuk Lee
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Patent number: 7871848Abstract: Provided are a semiconductor power module package and a method of fabricating the same. The semiconductor power module package includes a substrate, semiconductor chips arranged on a top surface of the substrate, and a temperature sensor mounted on a top surface of at least one of the semiconductor chips. The semiconductor chips and the temperature sensor are electrically connected to each other through leads. A sealing material covers the top surface of the substrate, the semiconductor chips, and the temperature sensor except for portions of the leads and a bottom surface of the substrate. The temperature sensor may include a thermistor, and the thermistor may include first and second electrode terminals connected to corresponding leads of the leads. A first wiring pattern may be in contact with the first electrode terminal, and a second wiring pattern may be in contact with the second electrode terminal.Type: GrantFiled: November 25, 2008Date of Patent: January 18, 2011Assignee: Fairchild Korea Semiconductor Ltd.Inventor: Keun-hyuk Lee
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Patent number: 7842545Abstract: Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semiconductor package includes an insulation metal substrate that includes a base member, an insulating layer disposed on the base member, and conductive patterns formed on the insulating layer. Semiconductor chips are arranged on the conductive patterns. Solder mask patterns are arranged on the conductive patterns to surround the semiconductor chips. Leads are electrically connected to the conductive patterns through wires. A sealing member is arranged on an upper surface and side surfaces of the substrate to cover portions of the leads, the wires, the semiconductor chips, and the solder mask patterns.Type: GrantFiled: December 18, 2009Date of Patent: November 30, 2010Assignee: Fairchild Korea Semiconductor, Ltd.Inventor: Keun-hyuk Lee
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Patent number: 7808103Abstract: Provided is a semiconductor package, and in particular a semiconductor package which is capable of electrically connecting to the outside without a lead.Type: GrantFiled: January 7, 2009Date of Patent: October 5, 2010Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Sung-min Park, Keun-hyuk Lee, Seung-Won Lim
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Publication number: 20100167470Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.Type: ApplicationFiled: February 9, 2010Publication date: July 1, 2010Applicant: Fairchild Korea Semiconductor, Ltd.Inventors: Keun-hyuk Lee, O-seob Jeon, Seung-won Lim
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Publication number: 20100165576Abstract: Provided are a power system module allowing a user's requirements to be easily met, and having economic practicality and high integration, and a manufacturing method thereof. The power system module includes a plastic case, a molding type power module package, a control circuit board, and at least one external terminal. The plastic case defines a bottom and a side wall. The molding type power module package is fixed to the bottom of the plastic case and includes at least a power device therein. The control circuit board is fixed to the side wall of the plastic case, includes at least a control device mounted thereon which is electrically connected to the power module package. The external terminal protrudes to outside the plastic case and is electrically connected to the control circuit board.Type: ApplicationFiled: March 11, 2010Publication date: July 1, 2010Applicant: Fairchild Korea Semiconductor, Ltd.Inventors: Keun-hyuk Lee, Seung-won Lim, Seung-han Paek, Sung-min Park
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Publication number: 20100140786Abstract: Provided is a semiconductor power module package including a bonding area on a direct bonding cupper (DBC) board. The semiconductor power module package includes: one or more semiconductor chips; a sealing member sealing the one or more semiconductor chips; a plurality of leads electrically connected to the one or more semiconductor chips and exposed from the sealing member; and an external bonding member electrically connected to the one or more semiconductor chips and electrically connecting an external circuit board exposed from the sealing member.Type: ApplicationFiled: December 7, 2009Publication date: June 10, 2010Applicant: FAIRCHILD KOREA SEMICONDUCTOR LTD.Inventors: Keun-hyuk LEE, Young-sun KO, Seung-won LIM, Man-kyo JUNG, Seung-yong CHOI
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Patent number: 7714428Abstract: A high power semiconductor package includes a substrate including a base metal layer, a base insulation layer formed on the base metal layer, and a plurality of conductive patterns formed on the base insulation layer. In one embodiment one or more high power semiconductor chips are mounted on the substrate, each including a plurality of bonding pads, one or more first package leads having end portions that are electrically connected to the corresponding conductive patterns, and a second lead having an end portion electrically which may be connected to either the base insulation layer or the base metal layer.Type: GrantFiled: December 6, 2007Date of Patent: May 11, 2010Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Keun-hyuk Lee, Seung-won Lim
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Patent number: 7706146Abstract: Provided are a power system module allowing a user's requirements to be easily met, and having economic practicality and high integration, and a manufacturing method thereof. The power system module includes a plastic case, a molding type power module package, a control circuit board, and at least one external terminal. The plastic case defines a bottom and a side wall. The molding type power module package is fixed to the bottom of the plastic case and includes at least a power device therein. The control circuit board is fixed to the side wall of the plastic case, includes at least a control device mounted thereon which is electrically connected to the power module package. The external terminal protrudes to outside the plastic case and is electrically connected to the control circuit board.Type: GrantFiled: April 5, 2007Date of Patent: April 27, 2010Assignee: Fairchild Korea Semiconductor LtdInventors: Keun-hyuk Lee, Seung-won Lim, Seung-han Paek, Sung-min Park
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Patent number: 7701048Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.Type: GrantFiled: May 3, 2007Date of Patent: April 20, 2010Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Keun-hyuk Lee, O-seob Jeon, Seung-won Lim
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Publication number: 20100093134Abstract: Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semiconductor package includes an insulation metal substrate that includes a base member, an insulating layer disposed on the base member, and conductive patterns formed on the insulating layer. Semiconductor chips are arranged on the conductive patterns. Solder mask patterns are arranged on the conductive patterns to surround the semiconductor chips. Leads are electrically connected to the conductive patterns through wires. A sealing member is arranged on an upper surface and side surfaces of the substrate to cover portions of the leads, the wires, the semiconductor chips, and the solder mask patterns.Type: ApplicationFiled: December 18, 2009Publication date: April 15, 2010Applicant: Fairchild Korea Semiconductor Ltd.Inventor: Keun-hyuk Lee
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Patent number: 7675148Abstract: Provided are a power module having a stacked flip-chip and a method of fabricating the power module. The power module includes a lead frame; a control device part including a control device chip; a power device part including a power device chip and being electrically connected to the lead frame; and an interconnecting substrate of which the control and power device parts are respectively disposed at upper and lower portions, and each of the control and power device chips may be attached to one of the lead frame and the interconnecting substrate using a flip-chip bonding method.Type: GrantFiled: February 28, 2008Date of Patent: March 9, 2010Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Seung-won Lim, O-Seob Jeon, Joon-seo Son, Keun-hyuk Lee, Yun-hwa Choi