Abstract: A semiconductor device includes a lower substrate, a memory cell structure including a wordline on the lower substrate, a bitline disposed on the lower substrate and intersecting the wordline, and a cell capacitor connected to the lower substrate, an upper substrate having a back side adjacent to the lower substrate and a front side opposite to the back side, a circuit element disposed on the front side of the upper substrate and overlapping the memory cell structure in a vertical direction, and a through via penetrating the upper substrate and electrically connecting the memory cell structure and the circuit element with each other.

Abstract: A display device and method of fabricating the same are provided. The display device includes a substrate and a thin-film transistor formed on the substrate. The thin-film transistor includes a lower gate conductive layer disposed on the substrate, and a lower gate insulating film disposed on the lower gate conductive layer The lower gate insulating film includes an upper surface and sidewalls. The thin-film transistor includes an active layer disposed on the upper surface of the lower gate insulating film, the active layer including sidewalls. At least one of the sidewalls of the lower gate insulating film and at least one of the sidewalls of the active layer are aligned with each other.

Abstract: A semiconductor memory device including an active pattern on a first substrate and comprising a first and second surfaces opposite to each other in a first direction, a data storage pattern between the active pattern and the first substrate and connected to a first surface of the active pattern, a bit line on the active pattern, connected to a second surface of the active pattern, and extending in a second direction, a word line on a sidewall of the active pattern, a second substrate, a peripheral gate structure on a first surface of the second substrate, a first connection wiring structure on the first surface of the second substrate and connected to the peripheral gate structure and bit line, a second connection wiring structure on a second surface of the second substrate and a through via penetrating the second substrate and connecting the first and second connection wiring structures.

Abstract: The present invention provides method and apparatus for purifying exhaust gas of a vessel and a vessel including the same, in which a risk for a vessel and crew of being exposed to ammonia gas used to collect carbon dioxide included in exhaust gas emitted from a vessel may be minimized and an ammonia solution may be recycled and reused to collect carbon dioxide, in order to satisfy regulations on discharge of exhaust gas by the IMO. Also, the present invention provides an apparatus 1000 for purifying exhaust gas of a vessel and a method of purifying exhaust gas of a vessel using the same, in which carbon dioxide and sulfur dioxide included in exhaust gas emitted from a vessel may be collected by using a reaction solution and may be changed into a substance that does not affect the environment so as to be stored and transported to land.

Abstract: A substrate cleaning apparatus includes a stage on which a substrate is placed, a support unit configured to support the substrate and to rotate the substrate, and a cleaning unit configured to spray a dual fluid to clean the substrate, wherein the cleaning unit may include a spray nozzle including a spray hole opened toward the stage and configured to spray a dual fluid through the spray hole, a cover that may include an inlet surrounding at least a partial area of an outer circumferential surface of the spray hole, that may surround at least a partial area of an outer circumferential surface of the spray nozzle, and that may be spaced apart from the spray nozzle by a predetermined distance, and an air flow passage formed in a space between the cover and the spray nozzle and through which air sucked from the inlet flows.

Abstract: The present specification discloses a DNA encoding and decoding method capable of converting and storing data more efficiently, wherein the DNA encoding method according to the present specification may convert binary data into sequence information using basic base values and degenerate base values, the degenerate base value may be a combination of at least two basic base values among four basic bases and the DNA decoding method according to the present specification may divide the basic base value and the degenerate base value into binary data according to base types for the same position in a plurality of DNA strands.

Abstract: A substrate processing apparatus includes: a conveyor belt configured to have an outer surface on which a bottom surface of a substrate is seated; and a polishing head unit configured to face an upper surface of the substrate, wherein the polishing head unit includes: a polishing head connected to a driver; a polishing pad configured to face the polishing head; a polishing pad fixing ring disposed between the polishing head and the polishing pad; and a temperature sensor configured to overlap the polishing pad fixing ring and to be spaced apart from the polishing pad fixing ring.

Abstract: A memory device according to an embodiment of the present disclosure may include a string including a plurality of memory cells and a select transistor connected between a conductive line and the plurality of memory cells; a peripheral circuit configured to perform an erase operation of the string; and a control logic configured to control the peripheral circuit to increase a voltage level of an erase voltage applied to the conductive line for a first time period from time one to later time two at a first voltage-time slope, and increase the voltage level of the erase voltage for a second time period from time two to later time three at a second voltage-time slope, during the erase operation, wherein the second voltage-time slope is greater than the first voltage-time slope.

Abstract: A memory controller having an improved operation speed controls a memory device including a plurality of memory blocks. The memory controller includes: a remaining count determiner configured to determine a remaining count that is a number of program and erase operations to be additionally performed in the memory device based on a program/erase count received from the memory device, a retention period calculator configured to determine a retention period based on a power-off time and a power-on time of the memory device and a read voltage determiner configured to generate a changed read voltage table based on a default read voltage table and a coefficient determined according to the remaining count, and determine a read voltage to be used in the memory device according to the retention period among read voltages included in the changed read voltage table.

Abstract: A substrate processing apparatus includes: a conveyor belt configured to have an outer surface on which a bottom surface of a substrate is seated; and a polishing head unit configured to face an upper surface of the substrate, wherein the polishing head unit includes: a polishing head connected to a driver; a polishing pad configured to face the polishing head; a polishing pad fixing ring disposed between the polishing head and the polishing pad; and a temperature sensor configured to overlap the polishing pad fixing ring and to be spaced apart from the polishing pad fixing ring.

Abstract: A method, system, and quiz server for providing a quiz and an advertisement simultaneously in an IMS chat is provided. The method includes creating a chat room from a mobile terminal while inviting a pre-registered quizbot as a chat participant, displaying a quiz and an advertisement within the chat room on the mobile terminal in the form of a chat message composed by the quizbot, and displaying, within the chat room, an answer of a certain chat participant with respect to the quiz, and inputting a result of determination of whether the answer is correct into the chat room by using the quizbot, displaying, within the chat room, the answer of the certain chat participant with respect to the quiz, and inputting a result of determination of whether the answer is correct into the chat room by using the quizbot.

Abstract: A memory system includes: a memory device; and a non-erase block management device suitable for determining, when an erase operation is performed on a first memory block included in the memory device, whether to perform a read operation on a second word line of a second memory block, according to a location of a first word line, which is a target word line for a read operation on the second memory block, wherein the second word line includes a target word line for a dummy read operation.

Abstract: A controller, for use in memory system, includes: a processor configured to control a read operation for a target memory area of a memory device in response to a read command received from a host; and an error correction circuit configured to perform an error correction operation on read data corresponding to the read operation, wherein the processor selects an optimum read voltage set among a plurality of read voltage sets in a read retry table, based on an erase write cycling (EW) number of the target memory area and a fail bit number of the read data.

Abstract: A memory controller having an improved operation speed controls a memory device including a plurality of memory blocks. The memory controller includes: a remaining count determiner configured to determine a remaining count that is a number of program and erase operations to be additionally performed in the memory device based on a program/erase count received from the memory device, a retention period calculator configured to determine a retention period based on a power-off time and a power-on time of the memory device and a read voltage determiner configured to generate a changed read voltage table based on a default read voltage table and a coefficient determined according to the remaining count, and determine a read voltage to be used in the memory device according to the retention period among read voltages included in the changed read voltage table.

Abstract: A method, system, and quiz server for providing a quiz and an advertisement simultaneously in an IMS chat is provided. The method includes creating a chat room from a mobile terminal while inviting a pre-registered quizbot as a chat participant, displaying a quiz and an advertisement within the chat room on the mobile terminal in the form of a chat message composed by the quizbot, and displaying, within the chat room, an answer of a certain chat participant with respect to the quiz, and inputting a result of determination of whether the answer is correct into the chat room by using the quizbot, displaying, within the chat room, the answer of the certain chat participant with respect to the quiz, and inputting a result of determination of whether the answer is correct into the chat room by using the quizbot.

Abstract: A memory system includes: a memory device; and a non-erase block management device suitable for determining, when an erase operation is performed on a first memory block included in the memory device, whether to perform a read operation on a second word line of a second memory block, according to a location of a first word line, which is a target word line for a read operation on the second memory block, wherein the second word line includes a target word line for a dummy read operation.

Abstract: A controller which controls an operation of a semiconductor memory device including a plurality of memory blocks. The controller includes a randomizer. The randomizer generates randomized data, based on a block address of a target memory block, and a program-erase count value or the target memory block. Accordingly, the performance of a memory system is improved.

Abstract: A memory device may include: a memory cell array comprising a plurality of search regions, each of the search regions comprising a plurality of group regions, each of the group regions comprising a flag cell, each flag cell comprising information indicating whether the corresponding group region is programmed; a voltage generator suitable for generating a read bias voltage for the memory cell array according to a voltage control signal; and a memory controller suitable for selecting a search region and controlling the voltage generator to adjust the read bias voltage based on information of flag cell of the selected search region when a read command is received, and controlling a read operation for the selected search region based on the adjusted read bias voltage.

Abstract: An operating method of a data storage device includes setting a first page access unit using a first page electrically coupled with a first word line of a first plane and a second page electrically coupled with a second word line of a second plane; and setting a second page access unit using a third page electrically coupled with a second word line of the first plane and a fourth page electrically coupled with a first word line of the second plane.

Abstract: A memory device may include: a memory cell array comprising a plurality of search regions, each of the search regions comprising a plurality of group regions, each of the group regions comprising a flag cell, each flag cell comprising information indicating whether the corresponding group region is programmed; a voltage generator suitable for generating a read bias voltage for the memory cell array according to a voltage control signal; and a memory controller suitable for selecting a search region and controlling the voltage generator to adjust the read bias voltage based on information of flag cell of the selected search region when a read command is received, and controlling a read operation for the selected search region based on the adjusted read bias voltage.