Patents by Inventor Kevin B. Traylor

Kevin B. Traylor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8181098
    Abstract: Methods and corresponding systems in a Viterbi decoder include computing a maximum likelihood (ML) path in a Viterbi trellis in response to executing a first Viterbi algorithm. Thereafter, one or more merge points are selected on the ML path in a second Viterbi algorithm, wherein the merge points each have a path metric difference, which is a difference between an ML path metric at the merge point and a non-surviving path metric at the merge point. Merge points are selected based upon relative path metric differences associated with nodes on the ML path. Next, alternate paths in the Viterbi trellis are computed based on the ML path with alternate paths substituted at corresponding merge points. A passing decoded bit sequence is output in response to passing an error check, wherein the passing decoded bit sequence is associated with one of the one or more alternate paths.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: May 15, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Christopher J. Becker, Kevin B. Traylor
  • Patent number: 8099657
    Abstract: Methods and corresponding systems in a Viterbi decoder include selecting an input symbol in an input block, wherein the input block has a plurality of input symbols, wherein each input symbol has a Boolean value, a quality value, and an associated stage, and wherein the selected symbol is selected based upon the quality value of the selected symbol relative to a quality value of other input symbols in the input block. Thereafter, the Boolean value of the selected symbol is complemented to produce a complemented symbol. The complemented symbol is substituted for the selected symbol to produce an alternate input block. A Viterbi algorithm is executed using the alternate input block to produce an alternate decoded bit sequence, which is then checked for errors using an error check. The alternate decoded bit sequence is output in response to the alternate decoded bit sequence passing the error check.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: January 17, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Christopher J. Becker, Kevin B. Traylor
  • Publication number: 20110280208
    Abstract: A method and system for wireless communications between base and mobile stations use reference signals transmitted from base stations prior transmission of data signals. The reference signals are used to determine propagation characteristics of communication channels between the base and mobile stations and optimize, in real time, parameters of receivers of the mobile stations for processing the following data signals. Applications of the invention include wireless communication systems compliant with OFDMA, 3GPP LTE, RFN-OFDMA, OFDM, TDMA, and the like communication protocols.
    Type: Application
    Filed: July 25, 2011
    Publication date: November 17, 2011
    Inventors: Leo G. Dehner, James W. McCoy, Kevin B. Traylor
  • Patent number: 7986933
    Abstract: A method and system for wireless communications between base and mobile stations use reference signals transmitted from base stations prior transmission of data signals. The reference signals are used to determine propagation characteristics of communication channels between the base and mobile stations and optimize, in real time, parameters of receivers of the mobile stations for processing the following data signals. Applications of the invention include wireless communication systems compliant with OFDMA, 3GPP LTE, RFN-OFDMA, OFDM, TDMA, and the like communication protocols.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: July 26, 2011
    Assignee: Apple Inc.
    Inventors: Leo G. Dehner, James W. McCoy, Kevin B. Traylor
  • Patent number: 7925862
    Abstract: A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and provides instructions (200, 220) to an instruction pipe (20) in the processor (12). Because the coprocessor (14) generated instructions are part of the standard instruction set of the processor (12), cache (70) coherency is easy to maintain. Also, circuitry (102) in coprocessor (14) may perform an operation on data while circuitry (106) in coprocessor (14) is concurrently generating processor instructions (200, 220).
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: April 12, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William C. Moyer, Kevin B. Traylor
  • Patent number: 7805590
    Abstract: A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and provides instructions (200, 220) to an instruction pipe (20) in the processor (12). Because the coprocessor (14) generated instructions are part of the standard instruction set of the processor (12), cache (70) coherency is easy to maintain. Also, circuitry (102) in coprocessor (14) may perform an operation on data while circuitry (106) in coprocessor (14) is concurrently generating processor instructions (200, 220).
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: September 28, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William C. Moyer, Kevin B. Traylor
  • Publication number: 20100011279
    Abstract: Methods and corresponding systems in a Viterbi decoder include selecting an input symbol in an input block, wherein the input block has a plurality of input symbols, wherein each input symbol has a Boolean value, a quality value, and an associated stage, and wherein the selected symbol is selected based upon the quality value of the selected symbol relative to a quality value of other input symbols in the input block. Thereafter, the Boolean value of the selected symbol is complemented to produce a complemented symbol. The complemented symbol is substituted for the selected symbol to produce an alternate input block. A Viterbi algorithm is executed using the alternate input block to produce an alternate decoded bit sequence, which is then checked for errors using an error check. The alternate decoded bit sequence is output in response to the alternate decoded bit sequence passing the error check.
    Type: Application
    Filed: July 11, 2008
    Publication date: January 14, 2010
    Inventors: Christopher J. Becker, Kevin B. Traylor
  • Publication number: 20090313314
    Abstract: A technique for performing a discrete Fourier transform (DFT) includes storing, in a single-port memory, multiple signal points. A first group of consecutive ones of the multiple signal points are fetched (from a first line of the single-port memory) to a first input register associated with a processor that includes multiple arithmetic units (AUs) that are each configured to perform multiply accumulate (MAC) operations. A second group of consecutive ones of the multiple signal points are then fetched (from a second line of the single-port memory) to a second input register associated with the processor. Selected pairs of the multiple signal points are then loaded (one from each of the first and second input registers for each pair) into the multiple arithmetic units during an initial butterfly stage. Radix-2 butterfly operations are then performed on the selected pairs of the multiple signal points (using the multiple AUs) to provide respective output elements.
    Type: Application
    Filed: June 17, 2008
    Publication date: December 17, 2009
    Inventors: JAYAKRISHNAN C. MUNDARATH, Leo G. Dehner, Kevin B. Traylor
  • Publication number: 20090313530
    Abstract: Methods and corresponding systems in a Viterbi decoder include computing a maximum likelihood (ML) path in a Viterbi trellis in response to executing a first Viterbi algorithm. Thereafter, one or more merge points are selected on the ML path in a second Viterbi algorithm, wherein the merge points each have a path metric difference, which is a difference between an ML path metric at the merge point and a non-surviving path metric at the merge point. Merge points are selected based upon relative path metric differences associated with nodes on the ML path. Next, alternate paths in the Viterbi trellis are computed based on the ML path with alternate paths substituted at corresponding merge points. A passing decoded bit sequence is output in response to passing an error check, wherein the passing decoded bit sequence is associated with one of the one or more alternate paths.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 17, 2009
    Inventors: Christopher J. Becker, Kevin B. Traylor
  • Publication number: 20090179697
    Abstract: An amplifier comprises first, second, and third modulators. The first modulator includes an input for receiving a first input signal, and an output for providing a first modulated output signal corresponding to the first input signal. The second modulator includes an input for receiving a second input signal, and an output for providing a second modulated output signal corresponding to the second input signal. The third modulator has an input for receiving a third input signal, and an output for providing a third modulated output signal corresponding to the third input signal and for providing a virtual ground. A first amplifier circuit is coupled to the outputs of the first and third modulators for driving a first load. A second amplifier circuit is coupled to the outputs of the second and third modulators for driving a second load.
    Type: Application
    Filed: January 11, 2008
    Publication date: July 16, 2009
    Inventors: Thomas J. Zuiss, Kevin B. Traylor
  • Patent number: 7554391
    Abstract: An amplifier comprises first, second, and third modulators. The first modulator includes an input for receiving a first input signal, and an output for providing a first modulated output signal corresponding to the first input signal. The second modulator includes an input for receiving a second input signal, and an output for providing a second modulated output signal corresponding to the second input signal. The third modulator has an input for receiving a third input signal, and an output for providing a third modulated output signal corresponding to the third input signal and for providing a virtual ground. A first amplifier circuit is coupled to the outputs of the first and third modulators for driving a first load. A second amplifier circuit is coupled to the outputs of the second and third modulators for driving a second load.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: June 30, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas J. Zuiss, Kevin B. Traylor
  • Patent number: 7539462
    Abstract: A multi-mode transmitter architecture is configurable for multiple modulation modes using either polar or polar-lite modulation. Multiplexed signal paths and reconfigurable components are controlled for performance in GMSK and EDGE burst modes. Polar-lite EDGE modulation is programmed by setting a multiplexer coupling a first amplitude modulated signal path with a frequency modulated signal path input to a dual-mode power amplifier for amplification of the combined EDGE transmission signal. In full-polar EDGE modulation, amplitude modulated signal is multiplexed into a second amplitude modulated signal path for A/D conversion and comparison with a polar feedback signal coupled from the power amplifier output. The resulting comparison is applied to a power control port of the power amplifier to amplitude modulate the EDGE transmission output. Multiplexers are configured to disconnect the amplitude modulated paths when operating in GMSK signaling for both full-polar and polar-lite modulation.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: May 26, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David S. Peckham, Richard B. Meador, Kevin B. Traylor
  • Patent number: 7469020
    Abstract: Systems, methods, and apparatus for reducing dynamic range requirements of a power amplifier in a wireless device are provided. An exemplary method may include modulating a symbol stream to generate a modulated waveform. The exemplary method may further include generating at least one pulse having a peak aligned with an anticipated position of a peak or a null corresponding to the modulated waveform, where the anticipated position of the a peak or the null corresponding to modulated waveform may be determined by detecting a transition in a phase or an amplitude of the modulated waveform.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: December 23, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: James Wesley McCoy, Kevin B. Traylor
  • Publication number: 20080232308
    Abstract: A method and system for wireless communications between base and mobile stations use reference signals transmitted from base stations prior transmission of data signals. The reference signals are used to determine propagation characteristics of communication channels between the base and mobile stations and optimize, in real time, parameters of receivers of the mobile stations for processing the following data signals. Applications of the invention include wireless communication systems compliant with OFDMA, 3GPP LTE, RFN-OFDMA, OFDM, TDMA, and the like communication protocols.
    Type: Application
    Filed: March 19, 2007
    Publication date: September 25, 2008
    Inventors: Leo G. Dehner, James W. McCoy, Kevin B. Traylor
  • Publication number: 20070300044
    Abstract: A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and provides instructions (200, 220) to an instruction pipe (20) in the processor (12). Because the coprocessor (14) generated instructions are part of the standard instruction set of the processor (12), cache (70) coherency is easy to maintain. Also, circuitry (102) in coprocessor (14) may perform an operation on data while circuitry (106) in coprocessor (14) is concurrently generating processor instructions (200, 220).
    Type: Application
    Filed: June 27, 2006
    Publication date: December 27, 2007
    Inventors: William C. Moyer, Kevin B. Traylor
  • Publication number: 20070300042
    Abstract: A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and provides instructions (200, 220) to an instruction pipe (20) in the processor (12). Because the coprocessor (14) generated instructions are part of the standard instruction set of the processor (12), cache (70) coherency is easy to maintain. Also, circuitry (102) in coprocessor (14) may perform an operation on data while circuitry (106) in coprocessor (14) is concurrently generating processor instructions (200, 220).
    Type: Application
    Filed: June 27, 2006
    Publication date: December 27, 2007
    Inventors: William C. Moyer, Kevin B. Traylor
  • Publication number: 20070300043
    Abstract: A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and the coprocessor (14). In one embodiment, a coprocessor (14) generates and provides instructions (200, 220) to an instruction pipe (20) in the processor (12). Because the coprocessor (14) generated instructions are part of the standard instruction set of the processor (12), cache (70) coherency is easy to maintain. Also, circuitry (102) in coprocessor (14) may perform an operation on data while circuitry (106) in coprocessor (14) is concurrently generating processor instructions (200, 220).
    Type: Application
    Filed: June 27, 2006
    Publication date: December 27, 2007
    Inventors: William C. Moyer, Kevin B. Traylor
  • Publication number: 20070290747
    Abstract: Systems and techniques are described for applying a polar bias modulation having a phase component and an amplitude component to a signal amplified by a power amplifier. The power amplifier (PA) has a plurality of amplifier gain stages and is configured to amplify an input to create an amplifier output signal. The input to the power amplitude is phase modulated based upon the phase component of the polar bias modulation, but need not be amplitude modulated. Amplitude modulation is provided by logic that includes a detector configured to receive an indication of the amplifier output as a feedback signal, a control module configured to generate a control signal based upon both the feedback signal and the amplitude component of the polar bias modulation, and a bias circuit configured to adjust a bias signal associated with at least one of the plurality of amplifier gain stages in response to the control signal.
    Type: Application
    Filed: May 31, 2006
    Publication date: December 20, 2007
    Inventors: Kevin B. Traylor, Richard B. Meador, George B. Norris, David S. Peckham
  • Publication number: 20030035636
    Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zint1 phase materials.
    Type: Application
    Filed: August 16, 2001
    Publication date: February 20, 2003
    Applicant: MOTOROLA, INC.
    Inventors: Kenneth A. Hansen, Kevin B. Traylor
  • Publication number: 20020181826
    Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates by forming a compliant substrate for growing the monocrystalline layers. One way to achieve compliancy includes first growing on a silicon wafer an accommodating buffer layer that is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. In this way, high speed devices can be fabricated along with integral silicon-based circuitry to provide an efficient, low-cost semiconductor structure. Moreover, I/O pins and their associated problems can be eliminated.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 5, 2002
    Applicant: MOTOROLA, INC.
    Inventors: Timothy Joe Johnson, Kevin B. Traylor, Duane C. Rabe