Patents by Inventor Kevin B. Traylor

Kevin B. Traylor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020179957
    Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer includes a layer of conductive metallic oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. A diode is formed on the overlying monocrystalline material layer, which is a gallium arsenide layer. Optionally, the accommodating buffer layer may include a non-conductive oxide layer on the conductive metallic oxide layer.
    Type: Application
    Filed: May 29, 2001
    Publication date: December 5, 2002
    Applicant: MOTOROLA, INC.
    Inventors: Kevin B. Traylor, James S. Irwin
  • Publication number: 20020180050
    Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 5, 2002
    Applicant: MOTOROLA, INC.
    Inventors: Barbara M. Foley, Duane C. Rabe, Kevin B. Traylor, Timothy Joe Johnson
  • Publication number: 20020179931
    Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystaline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
    Type: Application
    Filed: May 29, 2001
    Publication date: December 5, 2002
    Applicant: MOTOROLA, INC.
    Inventor: Kevin B. Traylor
  • Publication number: 20020179926
    Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 5, 2002
    Applicant: MOTOROLA, INC.
    Inventors: Barbara M. Foley, Duane C. Rabe, Kevin B. Traylor, Timothy Joe Johnson
  • Publication number: 20020181825
    Abstract: An integrated circuit that distributes its clock signals optically is provided. The integrated circuit may preferably include a plurality of digital CMOS circuits that communicate optically. The optical devices are preferably formed from compound semiconductor structures.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 5, 2002
    Applicant: MOTOROLA, INC.
    Inventors: Timothy Joe Johnson, Kevin B. Traylor, Duane C. Rabe, Barbara Foley Barenburg
  • Publication number: 20020181827
    Abstract: A system of integrated circuits including a plurality of optical semiconductor devices formed in silicon substrates such that the devices optically communicate with one another. The optical semiconductor devices are preferably formed from compound semiconductor structures. Each substrate may be formed in a single plane.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 5, 2002
    Applicant: MOTOROLA, INC.
    Inventors: Timothy J. Johnson, Kevin B. Traylor, William J. Ooms
  • Publication number: 20020179930
    Abstract: A composite semiconductor structure includes islands of noncompound semiconductor materials formed on a noncompound substrate, and an optical testing structure. In one embodiment, a scan chain runs through the noncompound substrate (and possibly also through the islands) and terminates in the islands at optical interface elements, one of which is an optical emitter and the other of which is an optical detector. A test device inputs test signals to, and reads test signals from, the scan chain by interfacing optically with the optical interface elements. In another embodiment, an optical detector is formed in the silicon substrate and an optical emitter is formed in the compound semiconductor material. A leaky waveguide communicating with the emitter overlies the detector, and detection by the detector of light emitted by the emitter is an indication of the absence of an intended circuit element between the detector and the leaky side of the waveguide.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 5, 2002
    Applicant: MOTOROLA, INC.
    Inventors: James S. Irwin, Clinton C. Powell, Timothy J. Johnson, Kevin B. Traylor, Duane C. Rabe, Barbara Foley Barenburg
  • Patent number: 6327313
    Abstract: A DC offset correction loop (200, 300) utilizes a peak estimator (218, 322) to determine peaks associated with a digital signal (238, 338). The peak estimator (218, 322) averages the peaks in order to estimate the DC offset. A summer (216, 326) sums the DC offset (242, 350) with the digital signal to produce a corrected output.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: December 4, 2001
    Assignee: Motorola, Inc.
    Inventors: Kevin B. Traylor, Jing Fang
  • Patent number: 6292047
    Abstract: A mixer circuit (400) for use with a multi-stage receiver (200) accepts a single ended or differential (i.e. balanced) input (401). A voltage to current converter (402) comprised of a single RF transistor coupled to the input (401) provides a single current node (404) having a current proportional to a received input. A switching network (408) employees a plurality of stages (406). Each stage (406) is connected to the current node (404) and further has a control line (A, B, C, D). A clock signal generator connected to the control lines (A, B, C, D) of the switching network stage (406), generates clock signals having a frequency equal to the frequency of the received RF input signal. The switching network (408) under control of the clock signals switches the current at a frequency y equal to the frequency of the received RF input signal to generate baseband I and Q signals. If the mixer (500) is differential, the balanced signal inputs (520) will be 180° out of phase, one to another.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: September 18, 2001
    Assignee: Motorola, Inc.
    Inventor: Kevin B. Traylor
  • Patent number: 6121819
    Abstract: A mixer circuit (400) for use with a multi-stage receiver (200) accepts a single ended or differential (i.e. balanced) input (401). A voltage to current converter (402) comprised of a single RF transistor coupled to the input (401) provides a single current node (404) having a current proportional to a received input. A switching network (408) employs a plurality of stages (406). Each stage (406) is connected to the current node (404) and further has a control line (A, B, C, D). A clock signal generator connected to the control lines (A, B, C, D) of the switching network stage (406), generates clock signals having a frequency equal to the frequency of the received RF input signal. The switching network (408) under control of the clock signals switches the current at a frequency equal to the frequency of the received RF input signal to generate baseband I and Q signals. If the mixer (500) is differential, the balanced signal inputs (520) will be 180.degree. out of phase, one to another.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: September 19, 2000
    Assignee: Motorola, Inc.
    Inventor: Kevin B. Traylor
  • Patent number: 6115589
    Abstract: A SONAD (110) control system (100) detects a received signal strength (RSSI) for a radio frequency (RF) signal (102), selects a threshold transfer function (400-404) in response thereto, generates a threshold control signal in response to the transfer function, and utilizes the threshold control signal to select the SONAD threshold value. During operation, the control system (100) decreases the attenuation of background noise levels for weak RF signals.
    Type: Grant
    Filed: April 29, 1997
    Date of Patent: September 5, 2000
    Assignee: Motorola, Inc.
    Inventors: Enrique Ferrer, Charles R. Ruelke, Andrew J. Webster, Kenneth A. Hansen, Rajesh H. Zele, Kevin B. Traylor
  • Patent number: 5623225
    Abstract: A demodulator (18) which receives digital representations of a received signal converts those signals into analog signals (53) in a pair of multiplying analog-to-digital converters (MDACs) (21, 22) The analog signals are then combined in combiner (26) by subtracting the first analog signal from the second analog signal (54). The summed signal is normalized (55) in quantizer (27). The output from the quantizer (27) is accumulated (56) in an n-bit accumulator (28) as regulated by a clock input (Fclock). The output of the accumulator (28) is used as a programming input (57) to the MDACs (21, 22).
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: April 22, 1997
    Assignee: Motorola, Inc.
    Inventor: Kevin B. Traylor
  • Patent number: 5418489
    Abstract: An apparatus and method is provided of recovering a frequency modulated signal having a first component of the frequency modulated signal at a zero-RF spectral location and a second component of the frequency modulated signal at a zero-RF spectral location in quadrature relationship to the first component. The method includes the steps of: upconverting and summing the first and second components to produce a reference signal (100), time delaying the first and second components, upconverting and summing the delayed, upconverted first and second components to produce a delayed reference signal (101) in quadrature relationship to the reference signal; limiting the reference and delayed signal (102); and exclusive or-ing (103) the limited reference and limited delayed signal.
    Type: Grant
    Filed: October 8, 1993
    Date of Patent: May 23, 1995
    Assignee: Motorola, Inc.
    Inventor: Kevin B. Traylor