Abstract: A test and measurement system is disclosed that includes an input for receiving a digital bus conducting a plurality of digital values, a display, and a memory. The memory stores hit frequencies for the digital values, and stores data indicating the digital values. The test and measurement system also includes at least one processor coupled to the display and the memory. The processor causes the display to depict the digital values and hit frequencies of the digital values by depicting persistence of the digital values over time and by depicting decay of the digital values over time.

Abstract: A test and measurement system is disclosed that includes an input for receiving a digital bus conducting a plurality of digital values, a display, and a memory. The memory stores hit frequencies for the digital values, and stores data indicating the digital values. The test and measurement system also includes at least one processor coupled to the display and the memory. The processor causes the display to depict the digital values and hit frequencies of the digital values by depicting persistence of the digital values over time and by depicting decay of the digital values over time.

Abstract: An apparatus and method for demultiplexing sampled data at a first data rate on a data line using a non-standard demultiplex mode is achieved by first demultiplexing the sampled data using a standard, factor of two, demultiplex mode, to produce n data lines at 1/n time the first data rate, and then down-converting n data lines to m data lines at 1/m times the first data rate to produce the non-standard demultiplex mode. As a specific example sampled data is demultiplexed using a standard 4× mode and then converted to a non-standard 3× mode.

Abstract: A calibration method for an oversampling acquisition system uses a digital calibration signal that has a period between edges that is unrelated to the period of a sample clock. The calibration signal in input in parallel to a plurality of samplers, each of which is clocked at a different time by a delayed version of the sample clock, to produce a plurality of sequential samples per sample clock period. Edge transitions of the calibration signal are counted that occur between adjacent ones of the samplers, and are accrued over an acquisition period to produce a plurality of edge counts. The edge counts are then processed to produce control signals to adjust the sample clock delay for each sampler so that the time intervals between the sequential samples are essentially uniform.

Abstract: A calibration method for an oversampling acquisition system uses a digital calibration signal that has a period between edges that is unrelated to the period of a sample clock. The calibration signal in input in parallel to a plurality of samplers, each of which is clocked at a different time by a delayed version of the sample clock, to produce a plurality of sequential samples per sample clock period. Edge transitions of the calibration signal are counted that occur between adjacent ones of the samplers, and are accrued over an acquisition period to produce a plurality of edge counts. The edge counts are then processed to produce control signals to adjust the sample clock delay for each sampler so that the time intervals between the sequential samples are essentially uniform.

Abstract: A plurality of digital samplers operating on a common signal under test (SUT) sample the SUT at a sample rate beyond that which guarantees monotonic sampling and non-overlapping setup and hold windows for adjacent samplers. Subsequent processing of the sample streams restores monotonicity and sample independence to provide thereby a very high effective sample rate.

Abstract: A range recognizer applies acquired data to the inputs of a plurality of boundary comparators simultaneously, treating an entire range of values for the data as a single continuum which is partitioned by a series of internal boundaries that are monitonically increasing. Each boundary comparator compares the value of the data with its unique boundary value and provides the results to a single range encoder logic to generate a single binary word as an encoded result indicative of the comparison for the entire range. An upper boundary result of one boundary comparator is combined with a lower boundary result of an adjacent higher boundary comparator prior to input to the single range encoder logic. The result is a reduction In the number of output pins required on an integrated circuit (IC) for reporting the encoded result for a corresponding plurality of range recognizers.

Abstract: A plurality of digital samplers operating on a common signal under test (SUT) sample the SUT at a sample rate beyond that which guarantees monotonic sampling and non-overlapping setup and hold windows for adjacent samplers. Subsequent processing of the sample streams restores monotonicity and sample independence to provide thereby a very high effective sample rate.

Abstract: An expanded WIRE-OR Bus structure has a first WIRE-OR Bus arrangement and a second WIRE-OR Bus arrangement. Each of the first and second WIRE-OR Bus arrangements have connected thereto at least one driver element and at least one receiver element. An intelligent bi-directional signal coupling circuit includes a buffer element, a bus arbiter, and a bus driver amplifier. The coupling circuit couples signals between the first WIRE-OR bus and the WIRE-OR second bus, and prevents signals originating on one of the WIRE-OR buses from being coupled back to the same WIRE-OR bus.

Abstract: Apparatus for data bus expansion between two instrument chassis comprises a first interface circuit, a connecting cable, and a second interface circuit. Detection circuitry in each interface circuit detects slot position. Slot position determines direction of address and data flow for each card. One of the first and second interface circuits is connected to a controller slot in a first chassis, and the other of the first and second interface circuits is connected to a non-controller slot in a second chassis. Bus interface circuitry for signal and identification are reconfigured in accordance with slot determination. As a result, the assembly formed by connection of two substantially identical interface cards with a cable, is symmetric and reversible.

Abstract: A range recognizer arrangement in accordance with the subject invention, requires only five IC pins to convey an encoded signal from a group of four range recognizers, and requires only twelve IC pins to convey an encoded signal from a group of over one thousand range recognizers. The subject range recognizer arrangement includes circuitry for combining and monotonically sorting all of the predetermined range boundaries, rather than treating each range recognizer as a separate unit. A range recognizer arrangement in accordance with the subject invention is suitable for use with test and measurement instruments such as a logic analyzer or the like.