Patents by Inventor Kevin J. Ash

Kevin J. Ash has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210263860
    Abstract: A method for maintaining statistics for data elements in a cache is disclosed. The method maintains a heterogeneous cache comprising a higher performance portion and a lower performance portion. The method maintains, within the lower performance portion, a ghost cache containing statistics for data elements that are currently contained in the heterogeneous cache, and data elements that have been demoted from the heterogeneous cache within a specified time interval. The method calculates a size of the ghost cache based on an amount of frequently accessed data that is stored in backend storage volumes behind the heterogeneous cache. The method alters the size of the ghost cache as the amount of frequently accessed data changes. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: February 22, 2020
    Publication date: August 26, 2021
    Applicant: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick
  • Publication number: 20210263862
    Abstract: A method for maintaining statistics for data elements in a cache is disclosed. The method maintains a heterogeneous cache comprising a higher performance portion and a lower performance portion. The method maintains, within the lower performance portion, a ghost cache containing statistics for data elements that are currently contained in the heterogeneous cache, and data elements that have been demoted from the heterogeneous cache within a specified time interval. The method maintains updates to the statistics in an update area within the higher performance portion. The method determines whether the updates have reached a specified threshold and, in the event the updates have reached the specified threshold, flushes the updates from the update area to the ghost cache to update the statistics. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: February 22, 2020
    Publication date: August 26, 2021
    Applicant: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick
  • Publication number: 20210263781
    Abstract: A method for dispatching tasks on processor cores based on memory access efficiency is disclosed. The method identifies a task and a memory area to be accessed by the task. The method may use one or more of a compiler, code knowledge, and run-time statistics to identify the memory area that is accessed by the task. The method identifies multiple processor cores that are candidates to execute the task and identifies a particular processor core from the multiple processor cores that provides most efficient access to the memory area. The method dispatches the task to execute on the particular processor core that is deemed most efficient. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: February 22, 2020
    Publication date: August 26, 2021
    Applicant: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew J. Kalos, Kevin J. Ash, Trung N. Nguyen
  • Patent number: 11093395
    Abstract: Provide a computer program product, system, and method for adjusting insertion points used to determine locations in a cache list at which to indicate tracks based on number of tracks added at insertion points. There are a plurality of insertion points to a cache list for the cache having a least recently used (LRU) end and a most recently used (MRU) end. Each insertion point of the insertion points identifies a track in the cache list. A plurality of tracks are indicated at positions in the cache list with respect to insertion points. For each track indicated at an insertion point of the insertion points, at least one insertion point counter for at least one insertion point with respect to the insertion point at which the track is indicated is incremented. A plurality of the insertion points are adjusted to point to different tracks in the cache list based on insertion point counters for the insertion points.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 11093399
    Abstract: Provided are a computer program product, system, and method for selecting resources to make available in local queues for processors to use. Each processor of a plurality of processors maintains a queue of resources for the processor to use when needed for processor operations. One of processors is selected. The selected processor accesses at least one available resource and includes the accessed at least one resource in the queue of the selected processor.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Publication number: 20210248082
    Abstract: A list of a first type of tracks in a cache is generated. A list of a second type of tracks in the cache is generated, wherein I/O operations are completed relatively faster to the first type of tracks than to the second type of tracks. A determination is made as to whether to demote a track from the list of the first type of tracks or from the list of the second type of tracks.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 12, 2021
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta
  • Publication number: 20210247930
    Abstract: A method for pinning selected volumes within a heterogeneous cache is disclosed. The method maintains a heterogeneous cache made up of a higher performance portion and a lower performance portion. A list of pinned volumes is received that are provided higher priority than other volumes within the heterogeneous cache. The method dedicates, within the lower performance portion, a storage area to accommodate the pinned volumes and prestages the pinned volumes within the storage area. In certain embodiments, an LRU list is maintained that indicates an order in which storage elements of the pinned volumes are demoted from the storage area. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: February 9, 2020
    Publication date: August 12, 2021
    Applicant: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kevin J. Ash, Beth A. Peterson
  • Publication number: 20210248079
    Abstract: A method to prevent starvation of non-favored volumes in cache is disclosed. In one embodiment, such a method includes storing, in a cache of a storage system, non-favored storage elements and favored storage elements. A cache demotion algorithm is used to retain the favored storage elements in the cache longer than the non-favored storage elements. The method designates a maximum amount of storage space that the favored storage elements are permitted to consume in the cache. In preparation to free storage space in the cache, the method determines whether an amount of storage space consumed by the favored storage elements in the cache has reached the maximum amount. If so, the method frees storage space in the cache by demoting favored storage elements. If not, the method frees storage space in the cache in accordance with the cache demotion algorithm. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: February 9, 2020
    Publication date: August 12, 2021
    Applicant: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Matthew G. Borlick, Beth A. Peterson
  • Patent number: 11086784
    Abstract: Provided are a computer program product, system, and method for invalidating track format information for tracks in cache. Demoted tracks demoted from the cache are indicated in a demoted track list. Track format information is saved for the demoted tracks. The track format information indicates a layout of data in the demoted tracks, wherein the track format information for the demoted tracks is used when the demoted tracks are staged back into the cache. An operation is initiated to invalidate a metadata track of the metadata tracks in the storage. Demoted tracks indicated in the demoted track list having metadata in the metadata track to invalidate are removed. The track format information for the demoted tracks having metadata in the metadata track to invalidate is removed.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos
  • Patent number: 11080149
    Abstract: Provided are a computer program product, system, and method for restoring tracks in cache. A restore operation is initiated to restore a track in the cache from a non-volatile storage to which tracks in the cache are backed-up. The non-volatile storage includes a current version of the track and wherein a previous version of the track subject to the restore operation is stored in a first location in the cache. A second location in the cache is allocated for the current version of the track to restore from the non-volatile storage. The data for the current version of the track is transferred from the non-volatile storage to the second location in the cache. Data for the track is merged from the second location into the first location in the cache to complete restoring to the current version of the track in the first location from the non-volatile storage.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: August 3, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 11080397
    Abstract: Provided are a computer program product, system, and method for using trap cache segments to detect malicious processes. A trap cache segment to the cache for data in the storage and indicated as a trap cache segment. Cache segments are added to the cache having data from the storage that are not indicated as trap cache segments. A memory function call from a process executing in the computer system reads data from a region of a memory device to output the read data to a buffer of the memory device. A determination is made as to whether the region of the memory device includes the trap cache segment. The memory function call is blocked and the process is treated as a potentially malicious process in response to determining that the region includes the trap cache segment.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Brian A. Rinaldi, Clint A. Hardy, Lokesh M. Gupta, Kevin J. Ash
  • Patent number: 11080622
    Abstract: Provided are a computer program product, system, and method for determining sectors of a track to stage into cache by training a machine learning module. A machine learning module that receives as input performance attributes of system components affected by staging tracks from the storage to the cache and outputs a staging strategy comprising one of a plurality of staging strategy indicating at least one of a plurality of sectors of a track to stage into the cache. A margin of error is determined based on a current value of a performance attribute and a threshold of the performance attribute. An adjusted staging strategy is determined based on the margin of error. The machine learning module is retrained with current performance attributes to output the adjusted staging strategy.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: August 3, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash
  • Publication number: 20210232973
    Abstract: Provided are a computer program product, system, and method for determining sectors of a track to stage into cache using a machine learning module. Performance attributes of system components affected by staging tracks from the storage to the cache are provided to a machine learning module. An output is received, from the machine learning module having processed the provided performance attributes, indicating a staging strategy indicating sectors of a track to stage into the cache comprising one of a plurality of staging strategies. Sectors of an accessed track that is not in the cache are staged into the cache according to the staging strategy indicated in the output.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Inventors: Lokesh M. Gupta, Kyle A. Anderson, Matthew G. Borlick, Kevin J. Ash
  • Patent number: 11074185
    Abstract: Provided are a computer program product, system, and method for adjusting a number of insertion points used to determine locations in a cache list at which to indicate tracks. Tracks added to the cache are indicated in a cache list. The cache list has a least recently used (LRU) end and a most recently used (MRU) end. In response to indicating in a cache list an insertion point interval number of tracks in the cache in a cache list, setting an insertion point to indicate one of the tracks of the insertion point interval number of tracks indicated in the cache list. Insertion points to tracks in the cache list are used to determine locations in the cache list at which to indicate tracks in the cache in the cache list.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Publication number: 20210224197
    Abstract: Provided are techniques for using a memory subsystem for a workload job. A section of a memory subsystem is allocated to a workload job, where the memory subsystem is comprised of a plurality of heterogeneous memory devices. In response to a track being modified for the workload job in a cache, it is determined that modified tracks have reached a threshold portion of the cache. In response to determining that the track exists in the section of the memory subsystem, data in the track in the section of the memory subsystem is overwritten with data in the track in the cache. in response to determining that the track does not exist in the section of the memory subsystem, the data in the track in the cache is copied to the track in the section of the memory subsystem, and the track is demoted from the cache.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: Lokesh Mohan GUPTA, Matthew G. BORLICK, Kevin J. ASH, Kyler A. ANDERSON
  • Publication number: 20210224200
    Abstract: Provided are a computer program product, system, and method for staging data from storage to a fast cache tier of a multi-tier cache in a non-adaptive sector caching mode in which data staged in response to a read request is limited to track sectors required to satisfy the read request. Data is also staged from storage to a slow cache tier of the multi-tier cache in a selected adaptive caching mode of a plurality of adaptive caching modes available for staging data of tracks. Adaptive caching modes are selected for the slow cache tier as a function of historical access ratios. Prestage requests for the slow cache tier are enqueued in one of a plurality of prestage request queues of various priority levels as a function of the selected adaptive caching mode and historical access ratios. Other aspects and advantages are provided, depending upon the particular application.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 22, 2021
    Inventors: Lokesh Mohan GUPTA, Kyler A. ANDERSON, Kevin J. ASH, Matthew G. BORLICK
  • Publication number: 20210224199
    Abstract: A method for improving cache hit ratios for selected storage elements within a storage system includes storing, in a cache of a storage system, non-favored storage elements and favored storage elements. The favored storage elements are retained in the cache longer than the non-favored storage elements. The method maintains a first LRU list containing entries associated with non-favored storage elements and designating an order in which the non-favored storage elements are evicted from the cache, and a second LRU list containing entries associated with favored storage elements and designating an order in which the favored storage elements are evicted from the cache. The method periodically scans the first LRU list for non-favored storage elements that have changed to favored storage elements, and the second LRU list for favored storage elements that have changed to non-favored storage elements. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: January 20, 2020
    Publication date: July 22, 2021
    Applicant: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Matthew G. Borlick, Beth A. Peterson
  • Patent number: 11068415
    Abstract: Provided are a computer program product, system, and method for using insertion points to determine locations in a cache list at which to move processed tracks. There are a plurality of insertion points to a cache list for the cache having a least recently used (LRU) end and a most recently used (MRU) end, wherein each insertion point of the insertion points identifies a track in the cache list. An insertion point of the insertion points is determined at which to move the processed track in response to determining that a processed track is indicated to move to the MRU end. The processed track is indicated at a position in the cache list with respect to the determined insertion point.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 11062232
    Abstract: Provided are a computer program product, system, and method for determining sectors of a track to stage into cache using a machine learning module. Performance attributes of system components affected by staging tracks from the storage to the cache are provided to a machine learning module. An output is received, from the machine learning module having processed the provided performance attributes, indicating a staging strategy indicating sectors of a track to stage into the cache comprising one of a plurality of staging strategies. Sectors of an accessed track that is not in the cache are staged into the cache according to the staging strategy indicated in the output.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: July 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash
  • Patent number: 11061818
    Abstract: A computer-implemented method, according to one embodiment, includes: in response to experiencing a power loss event, resupplying power to NVRAM which includes a write cache. In response to detecting that the NVRAM has experienced a failure event, the NVRAM is temporarily guarded from further use. Moreover, a portion of volatile memory is allocated to serve as a temporary write cache. The allocated portion of volatile memory is also cleared. A determination is made as to whether data is present in the write cache in the NVRAM, and in response to determining that data is present in the write cache, one or more volumes in memory which correspond to the data present in the write cache in the NVRAM are marked as having experienced data loss. Furthermore, a warning is sent which indicates that data loss has been experienced by the one or more marked volumes in the memory.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Todd C. Sorenson, Trung N. Nguyen, Kevin J. Ash, Louis A. Rasor